Proceedings Article | 23 May 2007
KEYWORDS: Switching, Picosecond phenomena, Very large scale integration, Digital electronics, Power supplies, Transistors, Logic, Interference (communication), Reliability, Clocks
The buffer insertion has been a mechanism widely used to increase the performances of advanced VLSI digital circuits
and systems. The driver or repeater used to this purpose has effect on the timing characteristics on the signal on the wire,
as propagation delay, signal integrity, transition time, among others. The power concerns related to buffering have also
received much attention, because of the low power requirements of modern integrated systems. In the same way, the
buffer insertion has strong impact on the reliability of synchronous systems, since the suited distribution of clock requires
reduced or controlled clock-skew, being the buffer and wire sizing, a crucial aspect. In a different way, buffer insertion has
been also used to reduce noise generation, especially in heavily loaded nets, since the inclusion of buffers help to desynchronize
signal transitions. However, the inclusion of buffers of inverters to improve one or more of these characteristics
have often negative effect on another parameters, as it happens in the average and peak of supply current. Mainly, the
inclusion of a buffer to reduce noise (peak power), via desynchronizing transitions, could introduce more dynamic consumption,
but reducing the short-circuit current because of the increment of signal slope. Thus, the average/peak current
optimization can be considered a design trade-off. In this paper, the mechanism to obtain an average/peak power optimization
procedure are presented. Selected examples show the feasibility of minimizing switching noise with negligible
impact on average power consumption.
