We present the design and testing of spaceflight multiplexing kinetic inductance detector (KID) readout electronics for the PRobe far-Infrared Mission for Astrophysics (PRIMA). PRIMA is a mission proposed to the 2023 NASA Astrophysics Probe Explorer (APEX) Announcement of Opportunity that will answer fundamental questions about the formation of planetary systems, as well as the formation and evolution of stars, supermassive black holes, and dust over cosmic time. The readout electronics for PRIMA must be compatible with operation at Earth-Sun L2 and capable of multiplexing more than 1000 detectors over 2 GHz bandwidth while consuming around 30 W per readout chain. The electronics must also be capable of switching between the two instruments, which have different readout bands,: the hyperspectral imager (PRIMAger, 2.5-5.0 GHz) and the spectrometer (FIRESS, 0.4-2.4 GHz). We present the driving requirements, design, and measured performance of a laboratory brassboard system.
More sophisticated non-dispersive infrared (NDIR) sensors for gas analysis have been developed in recent years, with many references in the literature. This technique is one of the most cost-effective methods to quantify the concentration of a target gas by measuring its absorption of infrared radiation. Dual channel thermopiles comprised of target and reference filter channels are reliably used to monitor the target gas for NDIR sensors. In recent years, commercial off-the-shelf quad-channel thermopiles with integrated passband infrared absorption filters have become available and enable up to three gas mixture detection and quantification, but there is no truly parallel readout circuit available for signal post processing. These sensors with their high sensitivity, fast response time and no cooling requirement makes them ideal candidates for applications that require monitoring multiple gases in real time. Usually, an NDIR sensor uses a cost-effective micro-controller for signal post processing, this limits the monitoring of multiple gases to a serial readout architecture. In this paper, we present a proof-of-concept non-dispersive infrared-red (NDIR) gas analyzer that has been realized with a quad-channel thermopile and a parallel readout circuitry consisting of a multi-channel digitizer (MCD) application specific integrated circuit (ASIC) and a field programmable gate array (FPGA). The parallel readout architecture will help considerably in the calibration schema. The NDIR gas analyzer will be used in a future space-based instrument application to ensure the safe transfer of sublimated volatiles from a comet sample containment system to a gas containment system within the operational pressure-temperature condition.
NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ΣΔ modulator. ΣΔ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.
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