Proceedings Article | 18 February 2022
KEYWORDS: Digital signal processing, Clocks, Optimization (mathematics), Associative arrays, Field programmable gate arrays, Computer aided design, Integrated circuit design, C++, Software engineering, Computer architecture
High-level synthesis technology is a technology for circuit design using high-level languages such as C, C++, or System C. This design method is suitable for algorithm engineers to implement calculation prototypes and is not suitable for hardware engineers to design circuits from the register transfer level. In addition, from the perspective of agile development and code reuse, C, C++, and System C are far from another hardware description language, Chisel. However, there are relatively few electronic design automation tools for Chisel, so we propose a circuit design flow based on CGRA hardware, in which Chisel designs the PE unit of CGRA. However, Chisel has few electronic design automation tools, so a circuit design flow based on CGRA is proposed. Dedicated data flow graph generation tools and typical coarse-grained reconfigurable arrays are implemented for this design flow. This article describes a design process based on CGRA and compares the design process with HLS through the DCT circuit design process. Through the experimental comparison of the two circuit implementation processes, it is found that, first of all, the correctness of the CGRA-based design process and the availability of data flow diagram generation tools. Secondly, from a design point of view, the use of Chisel will increase the overall development speed and increase the reusability of design files. Finally, from the perspective of toolchains, part of the tools in the new design process uses open-source toolchains, which reduces the cost of using toolchains and promotes the development of toolchains to a certain extent.
