Overlay errors, cut/block and line/space critical-dimension (CD) variations are the major sources of the edge-placement errors (EPE) in the cut/block patterning processes of complementary lithography when IC technology is scaled down to sub-10nm half pitch (HP). In this paper, we propose and discuss a modular technology to reduce the EPE effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. Preliminary results of altSAMP process development and material screening experiment are reported and possible material candidates are suggested. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below.
As optical lithography and conventional transistor structure are approaching their physical limits, 3D vertical gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of a vertical nanowire MOSFET and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement for high-density vertical nanowires/interconnects, and routing strategy are non-trivial challenges. In this paper, we shall discuss these critical issues for constructing standard cells using 3D vertical GAA nanowire MOSFETs and DSG MOSFETs. We redesigned the standard cells in Nangate Open Cell Library for 5nm node using vertical GAA nanowire MOSFETs and DSG MOSFETs. Experimental results verify the functionality of the proposed standard cell layout design approach.
To overcome the prohibitive barriers of edge-placement errors (EPE) in the cut/block/via step of complementary lithography, we propose a modular patterning approach by combining layout stitching, selective etching, and alternating-material self-aligned multiple patterning (altSAMP) processes. In this patterning approach, altSAMP is used to create line arrays with two materials alternatively which allow a highly selective etching process to remove one material without attacking the other, therefore more significant EPE effect can be tolerated in line-cutting step. With no need of connecting vias, the stitching process can form 2-D features by directly stitching two components of patterns together to create 2-D design freedom as well as multiple-CD/pitch capability. By adopting this novel approach, we can potentially achieve higher processing yield and more 2-D design freedom for continuous IC scaling down to 5 nm. We developed layout decomposition and synthesis algorithms for critical layers, and the fin/gate/metal layer from NSCU open cell library is used to test the proposed algorithms.
In this paper, a stitch database is built from various identified stitching structures in an open-cell layout library. The corresponding stitching yield models are developed for the hybrid optical and self-aligned multiple patterning (hybrid SAMP). Based on the concept of probability-of-success (POS) function, we first develop a single-stitching yield model to quantify the effects of overlay errors and cut-hole CD variations. The overhang distance designed in a stitching process (or its mean value μ) is found to be critical to the stitching yield performance and can be optimized using this yield model. We also investigate the physical significance of several process parameters such as half pitch (HP), standard deviation (σ) of the random overhang distribution, and cut-hole CD (CL). Our study shows that certain types of stitching yield are sensitive to σ and HP, while in general high yield can be achieved for a large number of stitching types we examined. To improve the yield of certain challenging stitching structures, various layout modification strategies are proposed and discussed.
To break through 1-D IC layout limitations, we develop computationally efficient 2-D layout decomposition and stitching techniques which combine the optical and self-aligned multiple patterning (SAMP) processes. A polynomial time algorithm is developed to decompose the target layout into two components, each containing one or multiple sets of unidirectional features that can be formed by a SAMP+cut/block process. With no need of connecting vias, the final 2-D features are formed by directly stitching two components together. This novel patterning scheme is considered as a hybrid approach as the SAMP processes offer the capability of density scaling while the stitching process creates 2-D design freedom as well as the multiple-CD/pitch capability. Its technical advantages include significant reduction of via steps and avoiding the interdigitating types of multiple patterning (for density multiplication) to improve the processing yield. The developed decomposition and synthesis algorithms are tested using 2-D layouts from NCSU open cell library. Statistical and computational characteristics of these public layout data are investigated and discussed.
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