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This paper presents the main characteristics of the CEA / LETI technology which is based on a monolithically integrated structure over a fully completed readout circuit from a commercially available 0.5 μm design rules CMOS line. The technology maturity will be illustrated by the results obtained at LETI/LIR and SOFRADIR on a 320 x 240 with a pitch of 45 μm. First improvement on device reliability and characterization results will be presented.
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