KEYWORDS: Design for manufacturing, Silicon, Polishing, Optical proximity correction, Back end of line, Metals, Failure analysis, Yield improvement, Logic, Manufacturing
A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic
process technologies. A noble technology combined a number of potential confliction of DFM techniques into a
comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon
diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are
optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and
advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve
manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented
in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5%
improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the
positive effect of the DFM techniques.
Automatic layout optimization is becoming an important component of the DfM work flow, as the number of
recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly
difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM
improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer
optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics,
while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained
intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base
Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements
(CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler
was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM
checking and by wafer yields.
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