KEYWORDS: Diffraction, Metals, Tin, Film thickness, Chemical mechanical planarization, Back end of line, Simulations, Spin on carbon materials, Overlay metrology, Signal intensity
Two of most important parameters for the integrated circuit manufacturing are linewidth and overlay. The linewidth uniformity is guaranteed by good exposure tooling, photoresist material, photomasks, Optical Proximity Correction (OPC), optimized patterning process, and good metrology. The linewidth metrology utilized the Scanning Electron Microscope (SEM) directly, which accuracy is entirely determined by the equipment. The overlay metrology quality, however, not only depends on the equipment performance, but can also depend on the substrate quality. There are two types of overlay measurement techniques, i.e., the Image Based Overlay (IBO) and the Diffraction Based Overlay (DBO). In this paper, we will focus our study on a 3 nm Complementary FET (CFET) metal layer overlay. The dimensions of a 3 nm logic design can be as small as 20~24 nm for the Fin Pitch (FP) and 36~48 nm for the Contacted Poly Pitch (CPP) and a On Product Overlay (OPO) of 2.5 nm is required. We will report our study on the DBO for the metal to metal overlay under typical 3 nm logic CFET design rules and a proposed film stack.
In advanced integrated circuit manufacturing technology, the introduction of nanosheet, forksheet, and Complementary Field Effect Transistor (CFET) architectures has created very complicated and dense vertical structures with dimensions as small as several nanometers and with many metallic layers which are not transparent to most optical wavelengths, posing a serious challenge to the metrology. We have provided a scatterometry study on a test pattern design based on the 3 nm logic design rules. Through a simulation study on typical dimensions, we have investigated various linewidths and contact depth with an algorithm based on the Rigorous Coupled Wave Analysis (RCWA).
As the dimensions of nanostructure rapidly shrink, the optical critical dimension (OCD) metrology, owing to its fast, non-destructive, and in-line-compatible features, has proved to be an effective tool to detect 3D periodic structure’s geometry at several nanometer-scale [1]. When the integrated circuit manufacturing enter the 3 nm technology node, Complementary FET (CFET) architectures, by utilizing shared gate for vertically stacked nanosheet n-FET and p-FET, have achieved notable reduction on average cell area, metal length and block-level area [2]. Because many metallic layers are not transparent to most optical wavelengths in CFET structures, and the gate oxide thickness and uniformity, the metal gate and inner spacer dimension uniformity are crucial during the process control [3], the sensitivity and precision of OCD metrology are very important and challenging. For instance, the inner spacers are formed by Atomic Layer Deposition (ALD) of spacer material on the recessed pockets of the SiGe superlattice formed by lateral over-etch during the source and drain etch process.The inner spacers insulate the metal gates and the source/drain terminals, which are decisive to the gate reliability and parasitic capacitance. Therefore, accurate control and measurement for inner spacers’ dimension uniformity is crucial to the manufacturing. In this paper, we will perform a study on the critical dimensions in CFET structures by using optical scatterometry simulation based on Rigorous Coupled Wave Analysis (RCWA). By tuning detection parameters, such as angle-of-incidence, illumination wavelength, polarization and scattering orders, we try to find an optimized parameter settings for measurement, and give recommendations for building OCD models of CFET structures.
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