Arbitrary shape detection, compared with analytic shape detection, plays a more significant role in machine vision for industrial automation. With the development of industrial automation, the requirements for low-delay detection and highprecision operation are gradually increasing. However, existing works on arbitrary shape detection pay more attention to detection accuracy, but few researchers attempt to achieve ultra-low detection delay, because of the limitation of the bandwidth between memory to CPU. This paper proposes clustering relative-vectors-based parallelization and temporal constraint for generalized Hough transform (GHT) algorithm compression to achieve the ultra-low delay process system, implemented on FPGA. By clustering relative vectors among closed edge pixels as a clustered vector, and defining a regularized R-Table structure, the parallelization of GHT has been increased. Moreover, fully utilizing the temporal information in high frame rate video leads to the compression of accumulator memory consumption, by confining the search widow and restricting the rotation range according to the detection result from the previous frame. The evaluation shows that the proposed architecture finishes the detection in VGA sized sequence with an ultra-low process delay of 1.851ms per frame.
High frame rate and ultra-low delay corner detection plays an increasingly important role in factory automated scenarios with a demand for accurate and robust corner features. However, classic intensity-based corner detection like the Harris method has limitations in determining corner types and parameter selection. Conventional contour-based corner detection like Chord to Triangular Arms Ratio (CTAR) method uses global level curve extraction based on the whole frame, leading to high delay. Achieving corner detection nearly simultaneous with capturing the same image provides a workable solution to minimize the delay. To modify the conventional detection methods which arbitrarily process any pixels within the scope of the entire input, a multi-line buffer based pipeline architecture is proposed. Using this pipeline, the whole frame is divided into lines processed independently. Junction connectivity analysis is proposed to define corner types based on the architecture. The proposed algorithm almost keeps the robustness (Average Repeatability of 0.5715, Localization Error of 0.4285) with the original CTAR method (AR of 0.5832, LE of 0.4374), better than the Harris method (AR of 0.5322, LE of 0.7324).
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