This paper describes the design-for-testability strategies integrated in a 0.35μm CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces.
After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented.
Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.
KEYWORDS: Modulators, Capacitors, Switches, Sensors, Signal to noise ratio, Computer aided design, Signal processing, Amplifiers, Transistors, Digital signal processing
This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C).
The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔΜ topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy.
The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography.
KEYWORDS: Data transmission, Resistance, Control systems, Analog electronics, Digital filtering, Oscillators, Capacitors, Modulation, Telecommunications, Amplifiers
This paper presents a CMOS mixed-signal MODEM ASIC for data transmission on the low-voltage power line. The circuit includes all the analog circuitry needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave filter
banks with PLL master VCO for tuning, and decision circuitry) plus the logic circuitry needed for control purposes. To allow the communication between the electrical household appliances and a remote unit to control them as well as to reduce the cost, an unique
mixed-signal ASIC, made of two parts, one operating at high frequencies and another operating at lower frequencies, has been designed. The High Frequencies Module must allow the connection with the external control systems and, to ensure reasonable robustness, has to be able to send and receive signals using at least two
different channels (to avoid local and temporary degradations of the communication). The Low Frequencies Module is needed to manage the indoors communication. This module enables the transmission of signals within distances between 50 and 100 meters with a speed
in the order of, but never less than, 100 bits/s. This link should be accomplished by using a frequency range in such a way that a maximum number of channels are disposable to allow the control of as many different in-house devices as possible. Again, to this end, two
different tunable channels have to be simultaneously available: one to control the quality of the signal and the other to allow the effective communication.
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