Selective Laser-induced Etching (SLE) is a laser-based process which enables the fabrication of three-dimensional parts from transparent materials with an enormous freedom of geometry and micrometer precision. A current research focus for the SLE process is the development and fabrication of ion traps made of fused silica for the ion-based approach of quantum computing. With the help of micrometer-sized electrically controllable components, ions are trapped inside an electrical field and their state is manipulated by means of laser radiation in the context of complex computing operations. Another research focus is the fabrication of fiber-chip couplers which are necessary components of smallest laser sources with the purpose to minimize and simplify the current complex experimental setup of a quantum computer. This work presents the current development of laser / SLE-based processes for the fabrication of microelectronic devices and quantum computing applications.
Selective Laser-induced Etching (SLE) is a manufacturing process which enables the fabrication of three-dimensional parts from transparent materials with unique freedom of geometry and high precision. First, the outer contour of the part is inscribed in the material using focused ultrashort pulsed laser radiation. Second, the modified design is exposed from the bulk material using wet chemical etching. We analyze the possibility of using SLE for the machining of next generation fused silica ion traps suitable for quantum computing. Such ion traps require an enhanced functionality in combination with reduced error sources and a reproducible manufacturing process. Ion trap designs with three-dimensional features in the micrometer regime are developed to meet these requirements. Challenges of the SLE process arising from the ion trap design and its dimensions are discussed. Different process strategies to fabricate single ion trap components as well as complete ion traps are examined. We demonstrate that next generation ion traps can be machined using SLE and outline the way towards a fabrication on wafer level.
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