In device overlay is an important contributor to the on-product overlay budget. Well known are overlay bias effects, i.e., differences between overlay targets and in-product features. These can be corrected by a non-zero overlay correction in the run-to-run system. In this paper, we examine micro-scale effects, which happen on scales of a few micrometers, for which there is not exposure tool correction possible. With a high-voltage SEM, we use a novel method to investigate both logic and memory wafers and identify several micro-scale effects that are a significant contributor to the on-product overlay budget. We characterize the behavior across the wafer and local variations. In the root cause analysis, we find several possible explanations including mask writer issues, local stress, and impact of the product pitch.
The performance of electrical circuits depends highly on the overlay of the actual device. However, overlay metrology is typically performed on dedicated non-device structures as proxy for device. In this paper, we show that an overlay metrology system based on high voltage scanning electron microscope (HV-SEM) can be used to measure the overlay errors of devices of any shape using a die-to-database (D:DB) algorithm. The D:DB algorithm uses the design-intent of multiple layers, in the form of database clips, to extract overlay errors for patterns of any shape. The D:DB algorithm can account for edge-over-edge effects as well as multiple visible layers at once. This enables accurate overlay measurements, even for complex devices, while simultaneously reporting overlay for multiple layer pairings. We show that this method of device measurement can be used to compare how the overlay error reported by different target designs matches the overlay error of the device structures itself.
Reticles for manufacturing upcoming 10nm and 7nm Logic devices will become very complex, no matter whether 193nm water immersion lithography will continue as main stream production path or EUV lithography will be able to take over volume production of critical layers for the 7nm node. The economic manufacturing of future masks for 193i, EUV and imprint lithography with further increasing complexity drives the need for multi-beam mask writing as this technology can overcome the influence of complexity on write time of today’s common variable shape beam writers. Local registration of the multi-beam array is a critical component which greatly differs from variable shape beam systems. In this paper we would like to present the local registration performance of the IMS Multi-Beam Mask Writer system and the metrology tools that enable the characterization optimization.
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