Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained.
To improve the productivity of nanoimprint lithography (NIL) in semiconductor manufacturing, we have developed spin-coating and flash imprint lithography (SC-FIL). Using a newly developed SC-FIL resist, we imprinted a 300-mm-wide whole wafer including partial fields. The cross-sectional image showed a well-shaped half-pitch dense line with a width of 26 nm. The mix-and-match overlay accuracy (3σ) was 3.9 nm in the X direction and 3.4 nm in the Y direction. Assuming Washburn’s model of capillary flow, we identified the unique defect-generation mechanism in SC-FIL and hence optimized the SC-FIL process for high throughput and low defect density. After optimizing the NIL, the multimodule NZ2C system with four imprint heads is expected to achieve a throughput of 124 wafers per hour and a defectivity of only 0.005 defects per cm2.
Nanoimprint lithography (NIL) has been received attention as an alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost, by transferring fine pattern of a template on to a resist layer by physical contact of template and resist followed by the resist curing. For more than a decade, we have been developing Jet and Flash Imprint Lithography (J-FIL) technology and challenging critical issues such as defect density, overlay, and throughput.
J-FIL is an efficient process for transferring template pattern having large variations in pattern density. However, it has the intrinsic limitation of lower throughput due to resist dispensing time prior to imprinting of every single field on the wafer and the spreading process of resist drops, slow diffusion of bubble trapped at the resist drop-boundaries. To eliminate the above mentioned steps and improve throughput, we have developed a spin coating NIL (SCN) process in which a uniform resist layer is spin coated on the entire wafer.
Identification of defect generation mechanism assuming Washburn’s model of capillary flow, has led us to optimize SCN process and thus achieving a higher throughput with lower defect density as compared to that of the J-FIL process. We will show the defect density and throughput performance of SCN process, and the possibility of introducing SCN in device production.
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