In this paper, successful fabrication of DLC thin films with tunable band gaps deposited by r.f. plasma-enhanced
chemical vapor deposition (RF-PECVD) under different bias voltages is reported. By Ultraviolet Transmission
Spectroscopy, it is revealed that the band gaps vary from 1.0eV to 2.1eV, which can cover the most important part of the
solar spectrum for terrestrial application solar cells. And the mechanism that band gaps of DLC films varied with the bias
voltages was analyzed by X-ray Photoelectron Spectroscopy (XPS). It is gotten that the different ratio of sp2/sp3 results
in different band gaps, which is apparently resulted by different bias voltage during the deposition process. The band gap
tends to have higher value at less sp2 content. The experiment results show that DLC multi-layer films can be used as an
effective absorber layer for thin films solar cells.
Silicon monolithically Optoelectronic Integrated Circuit (OEIC) designed in standard CMOS process has been gradually
applied. But Spice models of opticalelectronic devices such as photodetector can not be provided by IC manufactories in
OEIC design. A novel Spice model of photodetector is introduced for compatible-design of OEIC in this paper. An
N+/N-Well/P-Sub photodetector in standard CMOS process is described. The model of CMOS photodetector is
completely based on Hspice EDA design software. It includes optical current, dark current, junction capacitor, series
resistor, parallel resistor, and even noise characteristic. A four-terminal network structure is utilized to take the place of
the photodetector in the model. The whole model can be easily applied to OEIC design as a subcircuit. At 780nm
wavelength, the characteristics of the N+/N-Well/P-Sub photodiode fabricated in 0.5μm CMOS process are simulated
with the Spice model and tested. With a reverse bias of 2.5V, the measured and simulated responsivity is both about
0.25A/W, which indicates the availability of the model. Finally, the compatible-design of OEIC used for optical pickup
unit in optical storage system has been accomplished with the novel photodetector model.
Three kinds of structure photodetectors, N+/N-Well/P-Substrate, P+/N-Well/P-Substrate and finger N+/N-Well/P-Substrate, have been fabricated in CSMC 0.5μm CMOS process. The characteristics of different photodetectors are comparatively tested. The N+/N-Well/P-Substrate photodetector is choosed for construction of novel Spice model and fabrication of OEIC chip, considered about both high responsivity and good response speed. A novel Spice model of photodetector is introduced for compatible-design of OEIC. At 780nm and 2.5V reverse bias, the simulated responsivity based on the Spice model is 0.251A/W, close to the measured value 0.253A/W. Finally, a full CMOS monolithic OEIC is successfully accomplished with a gain of 38.1mV/μW in 780nm for optical-disc signal pickup.
Silicon photodetector is easy to be integrated with all kinds of Silicon IC to get monolithically OEIC. And the
photodetector array is also widely applied. A kind of
CMOS-process-compatible N+/N-Well/P-Sub photodetector and its
array are analyzed in this paper. Depended on the basic
time-dependent equations of photodetctor and analyzed by
Laplace transform method, the intrinsic frequency response characteristic is numerically calculated. The effect of reverse
bias voltage on spectral responsivity is also discussed. The photodetector is fabricated in 0.5μm CMOS process. At
780nm wavelength incident light, the measured and calculated responsivity are 0.253A/W and 0.251A/W, respectively.
The variety of measured responsivity with bias voltage is about 1.8mA/(W•V). At a reverse voltage of 5V, the maximum
dark current is 0.148nA. And the junction capacitance and -3dB frequency are also measured. The crosstalk factor of
photodetector with PN junction isolation and 5μm isolated space in CMOS technology is less than 5%.
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