KEYWORDS: Capacitance, Resistance, Computer programming, Chemical mechanical planarization, Manufacturing, 3D modeling, Neodymium, Very large scale integration, Lanthanum, Edge roughness
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to imrpove uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertion. We then give the first formulation of the Performance Impact Limited Fill (PIL-Fill) problem, and describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. We test our methods on two layout test cases obtained from industry. Compared with the normal fill method, our ILP-II method achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact, while maintaining identical quality of the layout density control.
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting area fill geometries in to the layout. We review previous research on single-layer fill for flat and hierarchical layout density control based on the Interlevel Dielectric CMP model. We also describe the recent combination of CMP physical modeling and linear programing for multiple-layer density control, as well as the Shallow Trench Isolation CMP model. Our work makes the following contributions for the Multiple-layer Interlevel Dielectric CMP model. First, we propose a new linear programming approach with a new objective for the multiple-layer fill problem. Second, we describe modified Monte-Carlo approaches for the multiple- layer fill problem. Comparisons with previous approaches show that the new linear programming method is more reasonable for manufacturability, and that the Monte-Carlo approach is efficient and yields more accurate results for large layouts. The CMP step in Shallow Trench Isolation (STI) is a dual-material polishing process, i.e., multiple materials are being polished simultaneously during the CMP process. Simple greedy methods were proposed for the non- linear problem with Min-Var and Min-Fill objectives, where the certain amount of dummy features are always added at a position with the smallest density. In this paper, we propose more efficient Monte-Carlo methods for the Min-Var objective, as well a improved Greedy and Monte-Carlo methods for the Min-Fill objective. Our experimental experience shows that they can get better solutions with respect to the objectives.
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