The Large Format Array-Controller (aLFA-C) development is sponsored by the ESA Cosmic Vision Program, resulting in an interfacing ASIC matched to the larger, clearer, lower-temperature focal plane arrays (FPA’s) demanded for future astronomical science missions [1]. The goal of this ASIC is to control and readout detector arrays and address the stringent operation requirements detector in a cryogenic infrared (IR) spacecraft environment [2]. Destined for use in space, the device is designed “radiation hard” throughout, and uses the imec DARE technology in the digital core and Caeleste’s “RH” in the analog part. The ASIC is capable of driving power supplies and bias lines, of delivering timing sequences, of acquiring the output signals of a wide range of FPA technologies, at temperatures even below 30K, with high accuracy; and of interfacing with the warm front-end electronics via a SpaceWire interface. For external use, the chip contains 12 regulators (LDO or normal regulator), 32 accurate voltage sources (VDAC), 8 programmable current sources (IDAC), 36 analog to digital converters(ADC) running at 100 kHz sampling rate, of which 32 can be interleaved to allow higher conversion rates on fewer channels, each input signal can be amplified and conditioned by a low noise programmable gain amplifier, and then digitized by a 16-bit successive approximation analog-to-digital converter (SAR-ADC). The programmable sequencer allows for 8 signal loops with a maximum word depth of 512, capable to work together with the embedded S8 microprocessor for more elaborate schemes. The specified operating range is 35 – 400K, yet the ASIC is found to be fully functional from 25K to room temperature (elevated temperature not yet tested). This paper presents an overview of the aLFA-C ASIC design with descriptions of its analog, mixed-signal and digital circuit blocks, test environment and preliminary test results.
For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This “ASIC” prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.
An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.