Optimizing standard cell design for quality

Chimin Yuan; Dave Tipple; Jeff Warner

doi:10.1117/12.2045660

28 March 2014 Optimizing standard cell design for quality

Chimin Yuan, Dave Tipple, Jeff Warner

Proceedings Volume 9053, Design-Process-Technology Co-optimization for Manufacturability VIII; 90530O (2014) https://doi.org/10.1117/12.2045660
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States

Abstract

To date, majority of the papers presented in the conference focused on how to print smaller transistors that run faster. In a different market such as safety-focused automotive market, “smaller and faster” are replaced by “tougher and living longer”. In such a market, a chip has to endure a wide range of operating temperature from -40C to 150C, and is required to have an extremely low field failure rate over 10+ years. There is a wide range of design techniques that can be deployed to improve the quality of a chip. In this paper, we present some of these design techniques that are related to the physical aspects of standard cells.

Citation Download Citation

Chimin Yuan, Dave Tipple, and Jeff Warner "Optimizing standard cell design for quality", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530O (28 March 2014); https://doi.org/10.1117/12.2045660

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