We experimentally realized a chip-based source-independent QRNG. The source-independent scheme provides a solution for the balance between the practical and device-independent QRNGs, which closes the security loopholes from the source, and can be easily realized with respect to the device-independent scheme based on loophole-free Bell test. For the measurement part, the imperfections of the detector are modeled and the practical loopholes in receiver side are thus closed. For the producibility, we use the Silicon-On-Illustrator (SOI) platform to integrate the optical path and detectors on chip. In this way, except for the local oscillator source, all the devices required by our QRNG scheme are integrated on a chip, which significantly promotes the miniaturization and scaling capabilities. The final generation rate is 15.6 Gbps, and the final random numbers well pass all the test items of NIST statistical tests, which demonstrates the practicability of a QRNG with source loophole-free, complete practical receiver modeling and chip-based devices.
For a high-speed and secure continuous-variable quantum key distribution (CV-QKD) system, privacy amplification (PA) plays an important role. To reduce the finite size effect, the input length of PA should be at least on the order of 10^8, 10^9, 10^10 when the transmission distance is about 50km, 80km, 100km, respectively. This leads to high computation complexity and large storage demand of the data, which is unfriendly to field programmable gate array (FPGA) implementation for its limited resource. In addition, the limited IO speed of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) restricts the implementation performance of PA. In this paper, we propose an effective way to access data based on DDR to improve the performance of PA. As a result, the reading time from DDR can be reduced, and it can eliminate the effect of the limited IO speed of DDR, so that PA can perform with multiple code-words. This can make full use of the resource of FPGA and increase the execution speed of PA. Besides, combining with the proposed method, an easier algorithm is used to decrease the complexity of calculations. Based on these methods, we realize PA with Toeplitz matrix based on FPGA and the experimental throughput is about 288Mbps when the input length is about 100Mbits.
The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
Continuous-variable quantum key distribution (CV-QKD) offers the advantages of high secret key rates in metropolitan areas. Optimization of modulation variance is an efficient method to improve the secret key rate of CVQKD system. However, in practical CV-QKD system, inevitable slight parameter fluctuation could occur after the modification of modulation variance, and controlling the modulation variance with arbitrary accuracy is also difficult. In this paper, we propose a two-step optimization for practical CV-QKD. The first step is to determine the optimal working state by combining the modulation variance optimization with error correction matrix optimization. The second step is to optimize the rate-adaptive reconciliation parameters to compensate the loss of secret key rate caused by inaccuracy modulation variance. Our results show that the secret key rate can be improved by 17.8% in comparison to one-step optimization method. Our method can be conveniently applied to CV-QKD protocol with homodyne and heterodyne detection, which will pave the way to the deployment of high stable and high performance for CV-QKD.
The throughput of error correction is the main bottleneck of continuous variable quantum key distribution (CV-QKD) postprocessing. Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA with limited precision can improve the decoding throughput significantly. However, the limited precision on FPGA results in the existence of residual error-bits after decoding, which lowers the secret key rate and restricts the application of high-rate real-time CVQKD system. In this paper, an efficient decoding scheme is proposed to erase the residual error-bits and decrease the frame errors rate (FER), where the decoding process into two stages and some values of initial Log Likelihood Ratio (LLR) are adjusted according to the proposed principles before starting the second-stage decoding. For the rates 0.2 and 0.1 LDPC codes, numerical results demonstrate that the proposed decoding scheme decreases the FER obviously and the throughputs of 152.47Mbps and 88.32Mbps are achieved, which can be applied to support high-speed CV-QKD system under transmission distance of 25km and 50km respectively.
Privacy amplification (PA) is an essential process for high-speed and real-time implementation of a continuous-variable quantum key distribution (CV-QKD) system. This work focuses on the improvement of the performance of PA, and we realize PA with Toeplitz matrix and accelerate it using fast Fourier transform (FFT) on graphic processing unit (GPU). Based on the architectural feature of FFT, we adjust its form of input length and obtained an average speed of PA about 2Gbps with input length ranges from 1Mbits to 128Mbits, which is length-adaptable to satisfy various requirements of CV-QKD systems at different transmission distances. Furthermore, we test this work with different compress ratios of PA, which can also achieve a high implementation speed around 2Gbps. With the method used in this paper, the requirements of PA for the high-speed and real-time CV-QKD system can be entirely satisfied.
Throughput of error correction is the bottleneck of the postprocessing for continuous-variable quantum key distribution system. In this paper, a shuffled iterative decoding method is proposed to reduce the number of iterations for error correction. For three typical code rate, i.e., 0.1, 0.05, 0.02, our results show that the maximum decoding speed is up to 72.86 Mbits/s, 53.96 Mbits/s and 42.45 Mbits/s, respectively, which significantly improves the real-time processing capacity of continuous-variable quantum key distribution system.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.