The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.
The cleaning requirements for EUV masks are more complex than optical masks due to the absence of available EUVcompatible pellicles. EUV masks must therefore be capable of undergoing more than 100 cleaning cycles with minimum impact to lithographic performance. EUV masks are created on substrates with 40 multilayers of silicon and molybdenum to form a Bragg reflector, capped with a 2.5nm-thick ruthenium layer and a tantalum-based absorber; during usage, both ruthenium and absorber are exposed to the cleaning process. The CrN layer on the backside is used to enable electrostatic clamping. This clamp side must also be free of particles that could impact printing and overlay, and particles could also potentially migrate to the frontside and create defects. Thus, the cleaning process must provide decent particle removal efficiencies on both front- and backside while maintaining reflectivity with minimal surface roughness change. In this paper, we report progress developing a concurrent patterned-side and clamped-side cleaning process that achieves minimal reflectivity change over 120 cleaning cycles, with XPS and EDS indicating the presence of ruthenium after 125 cleaning cycles. The change in surface roughness over 100 cleaning cycles is within the noise (0.0086nm) on a mask blank, and SEM inspection of 100nm and 200nm features on patterned masks after undergoing 100 cleaning cycles show no indications of ruthenium pitting or significant surface damage. This process was used on test masks to remove particles from both sides that would otherwise inhibit these masks from being used in the scanner.
The black border is a frame created by removing all the multilayers on the EUV mask in the region
around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a
wafer. Papers have documented its effectiveness. As the technology transitions into
manufacturing, the black border must be optimized from the initial mask making process through its
life. In this work, the black border is evaluated in three stages: the black border during fabrication,
the final sidewall profile, and extended lifetime studies.
This work evaluates the black border through simulations and physical experiments. The simulations
address concerns for defects and sidewall profiles. The physical experiments test the current black
border process. Three masks are used: one mask to test how black border affects the image
placement of features on mask and two masks to test how the multilayers change through extended
cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images
and simulated wafer effects.
By evaluating the black border from both a mask making perspective and a lifetime perspective, we
are able to characterize how the structure evolves. The mask data and simulations together predict
the performance of the black border and its ability to maintain critical dimensions on wafer. In this
paper we explore what mask changes occur and how they will affect mask use.
Through a series of experiments and simulation studies, this paper will explore the lithographic impact of absorber
thickness choice on an EUV photomask and highlight the trade-offs that exist between thick and thin absorbers.
Fundamentally, thinning the absorber modifies the intensity and phase of light reflected from the absorber while
simultaneously decreasing in the influence of feature edge topography. The decision to deploy a thinner absorber
depends on which imaging effect has a smaller impact after practical mitigation and correction strategies are employed.
These effects and the ability to correct for them are investigated by evaluating the absorber thickness impact on
lithographic imaging performance, stray light effects, topography effects, and CD variability. Although various tradeoffs
are described, it is generally concluded that thinning the absorber thickness below around 68 nm is not
recommended for a TaBN/TaBO absorber stack.
The lithography challenges posed by the 20 nm and 14 nm nodes continue to place strict minimum feature size
requirements on photomasks. The wide spread adoption of very aggressive Optical Proximity Correction (OPC) and
computational lithography techniques that are needed to maximize the lithographic process window at 20 nm and 14 nm
groundrules has increased the need for sub-resolution assist features (SRAFs) down to 50 nm on the mask. In addition,
the recent industry trend of migrating to use of negative tone develop and other tone inversion techniques on wafer in
order to use bright field masks with better lithography process window is requiring mask makers to reduce the minimum
feature size of opaque features on the reticle such as opaque SRAFs. Due to e-beam write time and pattern fidelity
requirements, the increased use of bright field masks means that mask makers must focus on improving the resolution of
their negative tone chemically amplified resist (NCAR) process.
In this paper we will describe the development and characterization of a high resolution bright field mask process that is
suitable for meeting 20 nm and early 14 nm optical lithography requirements. Work to develop and optimize use of an
improved chrome hard mask material on the thin OMOG binary mask blank1 in order to resolve smaller feature sizes on
the mask will be described. The improved dry etching characteristics of the new chrome hard mask material enabled the
use of a very thin (down to 65 nm) NCAR resist. A comparison of the minimum feature size, linearity, and through pitch
performance of different NCAR resist thicknesses will also be described. It was found that the combination of the
improved mask blank and thinner NCAR could allow achievement of 50 nm opaque SRAFs on the final mask.. In
addition, comparisons of the minimum feature size performance of different NCAR resist materials will be shown. A
description of the optimized cleaning processes and cleaning durability of the 50 nm opaque SRAFs will be provided.
Furthermore, the defect inspection results of the new high resolution mask process and substrate will be shared.
This paper focuses on the practical side of EUV mask metrology and use. Mask metrics such as film thickness, material
properties, feature profile, critical feature size, line edge/width roughness (LER/LWR) and defect levels are measured
and monitored on the mask. Any variability in mask properties will be transferred to wafer print results. EUV masks
have no pellicle and will be cleaned between exposures to extend use. This additional processing creates new
opportunity for modifications to the mask after qualification. This paper quantifies mask variability and the induced
change to printed wafer critical dimension (CD). The results are compared to the 56nm wafer pitch targets for CD and
LER. This EUV-specific effort is required to determine how close EUV masks are to meeting manufacturing
requirements and whether there are areas of development that require additional focus from the industry.
Extreme Ultraviolet Lithography (EUVL) offers the promise of dramatically improved resolution at the price of
introducing a complex web of new lithographic challenges. The most conspicuous departure from DUV lithography is
that exposure the wavelength is reduced from 193 to 13.5nm. Under exposure at this short EUV wavelength, all
materials absorb. Consequently the scanner optics and masks must be reflective and wafer exposure occurs in vacuum
without a pellicle to protect the mask. This represents a dramatic shift from the current DUV mask use case. For
example, the mask will have to be cleaned after exposure to remove contamination accumulated instead of being
protected for its lifetime by a transparent pellicle. The impact of cycling through the exposure tool and being cleaned
multiple times will be studied using particle inspection, scatterometry, reflectometry and AFM measurements. The
results will be used to identify contamination modes and to propose best practices for EUVL mask exposure.
The lithography challenges posed by the 22 nm node continue to place stringent requirements on photomasks.
The dimensions of the mask features continue to shrink more deeply into the sub-wavelength scale. In this
regime residual mask electromagnetic field (EMF) effects due to mask topography can degrade the imaging
performance of critical mask patterns by degrading the common lithography process window and by magnifying
the impact of mask errors or MEEF. Based on this, an effort to reduce the mask topography effect by
decreasing the thickness of the mask absorber was conducted. In this paper, we will describe the results of our
effort to develop and characterize a binary mask substrate with an absorber that is approximately 20-25% thinner
than the absorber on the current Opaque MoSi on Glass (OMOG) binary mask substrate.
For expediency, the thin absorber development effort focused on using existing absorber materials and deposition
methods. It was found that significant changes in film composition and structure were needed to obtain a
substantially thinner blank while maintaining an optical density of 3.0 at 193 nm. Consequently, numerous
studies to assess the mask making performance of the thinner absorber material were required and will be
described. During these studies several significant mask making advantages of the thin absorber were
discovered. The lower film stress and thickness of the new absorber resulted in improved mask flatness and up
to a 60% reduction in process-induced mask pattern placement change. Improved cleaning durability was
another benefit. Furthermore, the improved EMF performance of the thinner absorber [1] was found to have the
potential to relieve mask manufacturing constraints on minimum opaque assist feature size and opaque corner to
corner gap.
Based on the results of evaluations performed to date, the thinner absorber has been found to be suitable for use
for fabricating masks for the 22 nm node and beyond.
Lean manufacturing is a systematic method of identifying and eliminating waste. Use of Lean manufacturing techniques
at the IBM photomask manufacturing facility has increased efficiency and productivity of the photomask process. Tools,
such as, value stream mapping, 5S and structured problem solving are widely used today. In this paper we describe a
step-by-step Lean technique used to systematically decrease defects resulting in reduced material costs, inspection costs
and cycle time. The method used consists of an 8-step approach commonly referred to as the 8D problem solving
process. This process allowed us to identify both prominent issues as well as more subtle problems requiring in depth
investigation. The methodology used is flexible and can be applied to numerous situations. Advantages to Lean
methodology are also discussed.
During the development of optical lithography extensions for 32nm, both binary and attenuated phase shift Reticle
Enhancement Technologies (RETs) were evaluated. The mask blank has a very strong influence on the minimum feature
size and critical dimension (CD) performance that can be achieved on the finished reticle and can have a significant
impact on the ultimate wafer lithographic performance. Development of a suitable high resolution binary mask making
process was particularly challenging. Standard chrome on glass (COG) binary blanks with 70 nm thick chrome films
were unable to support the required minimum feature size, linearity, and through pitch requirements. Two alternative
mask blank configurations were evaluated for use in building high resolution binary masks: a binary (BIN) mask blank
based on the standard attenuated PSM blank and an Opaque MoSi on Glass (OMOG) mask blank consisting of a newly-
developed opaque MoSi [1]. Data comparing the total process bias, minimum feature size, CD uniformity, linearity,
through pitch, etch loading effects, flatness, film stress, cleaning durability and radiation durability performance of the
different binary and attenuated PSM mask blanks are reported. The results show that the new OMOG binary blank offers
significant mask performance benefits relative to the other binary and attenuated PSM mask blanks. The new OMOG
blank was the opaque mask blank candidate most capable of meeting 32nm binary mask fabrication requirements..
Sub-Resolution Assist Features (SRAFs) are typically the smallest features on a photomask and amplify many of the
challenges in mask manufacturing. During the initial stages of process development, resist feature adhesion is the
dominate damage mechanism. Throughout mask fabrication, the influence of inherent material properties and wet
processing can eventually delaminate SRAFs. The various mechanisms that cause SRAF damage will be presented
systematically. Process optimization steps to address the failure mechanisms will be presented. Data illustrating the
improved process window for small features will be included.
As optical lithography is extended for use in manufacturing 45 nm devices, it becomes increasingly important to
maximize the lithography process window and enable the largest depth of focus possible at the wafer stepper.
Consequently it is very important that the reticles used in the wafer stepper be as flat as possible. The ITRS roadmap
requirement for mask flatness for 45 nm node is 250 nm. To achieve this very tight reticle flatness requirement, the stress
of each film present on the mask substrate must be minimized. Another key reticle specification influenced by film stress
on the mask blank is image placement. In this paper, we will describe the development and detailed characterization of a
new low stress Molybdenum Silicide (MoSi) film for use in manufacturing 45 nm node critical level attenuated phase
shift masks to be used in 193 nm immersion lithography. Data assessing and comparing the cleaning durability, mask
flatness, image placement, Critical Dimension (CD) performance, dry etch properties, phase performance, and defect
performance of the new low stress MoSi film versus the previous industry standard A61A higher stress MoSi attenuator
film will be described. The results of our studies indicate that the new low stress MoSi film is suitable for 45 nm mask
manufacturing and can be introduced with minimal changes to the mask manufacturing process.
Existing cleaning technology using sulfuric acid based chemistry has served the mask industry quite well over the years. However, the existence of residue on mask surfaces is becoming more and more of a problem at the high energy wavelengths used in lithography tool for wafer manufacturing. This is evident by the emergence of sub-pellicle defect growth and backside hazing issues. A large source of residual contamination on the surface of masks is from the mask manufacturing process, particularly the cleaning portion involving sulfuric acid. Cleaning strategies can be developed that eliminate the use of sulfuric acid in the cleaning process for advanced photomasks and alternative processes can be used for cleaning masks at various stages of the manufacturing process. Implementation of these new technologies into manufacturing will be discussed as will the resulting improvements, advantages, and disadvantages over pre-existing mask cleaning processes.
As new technologies are developed for smaller linewidths, the specifications for mask cleanliness become much stricter. Not only must the particle removal efficiency increase, but the largest allowable particle size decreases. Specifications for film thickness and surface roughness are becoming tighter and consequently the integrity of these films must be maintained in order to preserve the functionality of the masks. Residual contamination remaining on the surface of the mask after cleaning processes can lead to subpellicle defect growth once the mask is exposed in a stepper environment. Only during the last several years, has an increased focus been put on improving mask cleaning. Over the years, considerably more effort has been put into developing advanced wafer cleaning technologies. However, because of the small market involved with mask cleaning, wafer cleaning equipment vendors have been reluctant to invest time and effort into developing cleaning processes and adapting their toolset to accommodate masks. With the advent of 300 mm processing, wafer cleaning tools are now more easily adapted to processing masks. These wafer cleaning technologies may offer a solution to the difficulties of mask cleaning and need to be investigated to determine whether or not they warrant continued investigation. This paper focuses on benchmarking advanced wafer cleaning technologies applied to mask cleaning. Ozonated water, hydrogenated water, super critical fluids, and cryogenic cleaning have been investigated with regards to stripping resist and cleaning particles from masks. Results that include film thickness changes, surface contamination, and particle removal efficiency will be discussed.
At the challenging ground rules required for 90 nm and 65 nm photomask production, new types of photomask defects are becoming increasingly prevalent. This paper discusses one particular new defect type found on critical 90 nm embedded attenuated phase-shift masks (EAPSMs). These defects had varying transmission characteristics depending on the wavelength used for analysis. Given that photomask inspection wavelength has historically lagged behind lithography wavelength, this type of defect can go undetected and poses a grave risk to wafer lithography yield. Detection and characterization methodologies will be presented along with aerial image analysis and wafer print evaluation results.
Fabrication of EUVL masks requires formation of both a repair buffer layer and an EUV absorber layer on top of a molybdenum/silicon (Mo/Si) multilayer coated mask blank. Alteration of the Mo/Si multilayer during etch, repair or cleaning of the EUVL mask can be detrimental to the reflectivity and thus the functionality of the final mask. IBM’s Next Generation Lithography (NGL) group has reported on EUVL mask fabrication based on an absorber of low stress chromium (Cr) and a buffer layer of silicon dioxide (SiO2). Due to poor etch selectivity between SiO2 and the underlying silicon capping layer, the finished masks had non-uniform and reduced EUV reflectivity after processing. This led to the development of an alternative absorber stack combination of an absorber layer of low stress TaNx on a buffer layer of low stress Cr. This paper describes the improved reflectivity uniformity of this type of mask along with several aspects of mask quality, such as CD control and image placement.
Electron projection lithography (EPL) is a promising candidate for the next generation lithography choice. There are several advantages to EPL, such as a large depth of focus and a lower relative mask cost. Significant challenges also face this technology, including the limitation of the membrane format of the mask. One of the obstacles with the membrane format is image placement distortions, which can be very sensitive to the stress of the membrane as well as the pattern density. This paper studies how the stress of various types of films effects image placement distortions, as well as examines the effect of final mask cleans on image placement distortions.
The Next Generation Lithography (NGL) Mask Center of Competency (MCoC) has been developing mask technology to support all of the major next generation lithographies for several years. Cross-cutting process development has been applied to generate progress in both the membrane and reflective mask formats. The mask technology has been developed to early capability stage for all of the mask formats. Proximity x-ray masks, although only for certain niche applications, are a very developed mask format. This information has been used to produce electron beam projection masks, in both continuous membrane and stencil formats, and extreme ultraviolet lithography masks. In this paper, we discuss the status of the lithography technology development and the obstacles that remain between the current early development capability and the availability for manufacturing.
The next generation lithography, either electron or photon based, will be first introduced on critical levels for device manufacture. These levels have different requirements for difficulty of meeting image size uniformity, image placement, and patterning requirements on masks. Membrane masks are needed for electron projection lithography (EPL), and the fabrication of membrane masks generates new requirements such as the need for complementary mask pairs for stencil masks. In this paper, we discuss experiments for fabricating EPL masks for device levels.
The extreme ultraviolet lithography (EUVL) mask differs from its predecessors in many ways. The most significant change is that the EUVL mask is reflective, introducing many new film layers and mask sensitivities. An additional complication is the small linewidths associated with the 45-nm node that is targeted for EUVL mask introduction. This paper concentrates on the physical specifications associated with the 45-nm node EUVL mask. Relative to current masks, the defect levels must be lower and the film quality must be higher. Standard cleans may be incompatible with new mask requirements. To understand the development requirements, the cleaning efficiency, film removal, film roughness, defect levels and film reflectivity are quantified on both EUVL mask film monitors and EUVL masks. Target specifications and measured properties of the 45-nm node masks will be compared.
Fabricating masks for extreme ultraviolet lithography is challenging. The high absorption of most materials at 13.4 nm and the small critical dimension (45 nm) at the target insertion node force many new features, including reflective mask design, new film choices, and stringent defect specifications. Fabrication of these masks requires the formation and patterning of both a repair buffer layer and an EUV absorber layer on top of a molybdenum/silicon multi-layer substrate. IBM and Photronics have been engaged in developing mask processing technology for x-ray, electron beam projection and extreme ultraviolet lithographies at the Next Generation Lithography Mask Center of Competency (NGL-MCoC) within IBM's mask facility at Essex Junction, Vermont. This paper describes recent results of mask fabrication on 6 x 6 x 1/4 inch EUVL substrates (quartz with molybdenum silicon multi-layers) at the MCoC. Masks fabricated with high and low-stress chromium and externally deposited chromium absorber films are compared. In particular, etch characteristics, image size, image placement, line edge roughness, and defect levels are presented and compared. Understanding the influence of the absorber film characteristics on these parameters will enable us to optimize the effectiveness of a given absorber film or to select acceptable alternatives.
Fabricating masks for extreme ultraviolet lithography (EUVL) is challenging. New design features have been introduced because of the high absorption of most materials at 13.4 nm and the small critical dimension (70 nm and below). The novel mask features introduced with EUVL include the reflective design, new film combinations, and stringent defect specifications. This paper focuses on one aspect of the mask build process that must be detected, understood, and minimized: defects. We obtain our EUV mask blanks with the multi-layers already in place. While the deposition of usable Mo/Si multi-layers is a challenge in itself, our pursuit of a clean EUV mask process begins with the buffer layer. From that point, the basic mechanics of the mask build is: deposit the buffer layer, deposit the absorber layer, apply and pattern the resist, and etch the absorber. The buffer layer is left to protect the multi-layers during inspection and repair. Careful attention to cleaning, inspection, and repair will be required to meet the ITRS Roadmap's 55 nm maximum defect size (at the 70 nm node). Our inspection methodology, defect data and repair options will be presented in detail.
Masks for electron projection lithography require the use of thin membrane structures due tot he short scattering range of electrons in solid materials. The two leading mask formats for electron projection lithography are the continuous membrane scatterer mask and the stencil mask. The reduced mechanical stability of the membranes used for electron projection masks relative to conventional optical masks leads to increased levels of process induced image placement distortions. This paper evaluates the image placement distortions due to the pattern transfer processes on the continuous membrane mask format. Image placement was measured from both a cross-mask and intramembrane perspective to evaluate the effects of different patterns, pattern densities and density gradients on the observed image placement and the experimental results obtained were then compared to those predicted by finite element modeling.
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