This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode
sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively
Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides
streamlined inter-processor connections with deterministically high performance. Software programmability, scalability,
ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant
advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods
of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming
model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They
exchange data and control through a network of self-synchronizing channels. A common application design pattern on
this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically
configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and
decompression, network processing, and graphics applications.
KEYWORDS: Ultrasonography, Phased arrays, Transducers, Analog electronics, Digital signal processing, Computer programming, Java, Array processing, Field programmable gate arrays, Algorithm development
Digital beamforming has been widely used in modern medical ultrasound instruments. Flexibility is the key advantage
of a digital beamformer over the traditional analog approach. Unlike analog delay lines, digital delay can be
programmed to implement new ways of beam shaping and beam steering without hardware modification. Digital
beamformers can also be focused dynamically by tracking the depth and focusing the receive beam as the depth
increases. By constantly updating an element weight table, a digital beamformer can dynamically increase aperture size
with depth to maintain constant lateral resolution and reduce sidelobe noise. Because ultrasound digital beamformers
have high I/O bandwidth and processing requirements, traditionally they have been implemented using ASICs or
FPGAs that are costly both in time and in money.
This paper introduces a sample implementation of a digital beamformer that is programmed in software on a Massively
Parallel Processor Array (MPPA). The system consists of a host PC and a PCI Express-based beamformer accelerator
with an Ambric Am2045 MPPA chip and 512 Mbytes of external memory. The Am2045 has 336 asynchronous RISCDSP
processors that communicate through a configurable structure of channels, using a self-synchronizing
communication protocol.
This Poster Exhibit examines some of the criteria used to evaluate high resolution display systems. These systems have several applications including medical imaging, prepress, and image exploitation. Criteria examined are number of shades of gray, bandwidth, focus, smearing, and ghosting. These each constitute a way of characterizing the quality of the image, allowing us to go beyond an expression of "looks pretty nice." The display systems used are 2048x2560 grayscale monitors, driven by a graphics card that plugs into one of the PCI slots in a computer or workstation.
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