KEYWORDS: Extreme ultraviolet, Data modeling, Photomasks, Scattering, Monte Carlo methods, Point spread functions, Process modeling, Electron beams, Tantalum, Chromium
In electron beam writing on EUV mask, it has been reported that CD linearity does not show simple signatures as
observed with conventional COG (Cr on Glass) masks because they are caused by scattered electrons form EUV mask
itself which comprises stacked heavy metals and thick multi-layers. To resolve this issue, Mask Process Correction
(MPC) will be ideally applicable. Every pattern is reshaped in MPC. Therefore, the number of shots would not increase
and writing time will be kept within reasonable range. In this paper, MPC is extended to modeling for correction of CD
linearity errors on EUV mask. And its effectiveness is verified with simulations and experiments through actual writing
test.
This paper investigates the application of source-mask optimization (SMO) techniques for 28 nm logic device and
beyond. We systematically study the impact of source and mask complexity on lithography performance. For the source,
we compare SMO results for the new programmable illuminator (ASML's FlexRay) and standard diffractive optical
elements (DOEs). For the mask, we compare different mask-complexity SMO results by enforcing the sub-resolution
assist feature (SRAF or scattering bar) configuration to be either rectangular or freeform style while varying the mask
manufacturing rule check (MRC) criteria. As a lithography performance metric, we evaluate the process windows and
MEEF with different source and mask complexity through different k1 values. Mask manufacturability and mask writing
time are also examined. With the results, the cost effective approaches for logic device production are shown, based on
the balance between lithography performance and source/mask (OPC/SRAF) complexity.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection results on test and production reticles have been validated with AIMSTM.
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection result has been validated with AIMSTM.
The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity
errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks
become more significant in the overall lithography error budget. To address this, we have carried out a study that:
(1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error
models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC
can significantly reduce mask errors with minimal increase in writing overhead.
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