Paper
14 September 2001 Application of full-chip level optical proximity correction to memory device with sub-0.10-μm design rule and ArF lithography
Author Affiliations +
Abstract
Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hyoung-Soon Yune, Hee-Bom Kim, Wan-Ho Kim, Chang-Nam Ahn, Young-Mog Ham, and Ki-Soo Shin "Application of full-chip level optical proximity correction to memory device with sub-0.10-μm design rule and ArF lithography", Proc. SPIE 4346, Optical Microlithography XIV, (14 September 2001); https://doi.org/10.1117/12.435724
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KEYWORDS
Optical proximity correction

Photomasks

Lithography

Critical dimension metrology

Semiconducting wafers

Model-based design

Data modeling

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