Mr. Wan Ho Kim Profile

Wan Ho Kim

Account Technology Manager at Siemens EDA

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Publications (4)

Proceedings Article | 23 March 2011 Paper

Feasibility study on the mask compensation of gate CD non-uniformity caused by etching process

Wan Ho Kim, Ek Jen Yet, Siew Ing Yet, Boon Chun Lee

Proceedings Volume 7973, 797331 (2011) https://doi.org/10.1117/12.879197

KEYWORDS: Etching, Critical dimension metrology, Photomasks, Silicon, Optical proximity correction, Lithography, Manufacturing, Semiconducting wafers, Plasma etching, Photoresist materials

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Proceedings Article | 30 July 2002 Paper

Double-exposure strategy using OPC and simulation and the performance on wafer with sub-0.10-um design rule in ArF lithography

Se-Young Oh, Wan-Ho Kim, Hyoung-Soon Yune, Hee-Bom Kim, Seo-Min Kim, Chang-Nam Ahn, Ki-Soo Shin

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474541

KEYWORDS: Optical proximity correction, Lithography, Semiconducting wafers, Double patterning technology, Optical lithography, Reticles, Device simulation, Electroluminescence, Image processing, Lithographic illumination

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As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one region's overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.

Proceedings Article | 30 July 2002 Paper

Defect printability and specification of ArF mask in repeating feature

Wan-Ho Kim, Won-Kwang Ma, Hee-Bom Kim

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474518

KEYWORDS: Photomasks, Semiconducting wafers, Inspection, Printing, Lithography, Manufacturing, Photoresist processing, Cadmium, Diffusion, Semiconductors

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Proceedings Article | 14 September 2001 Paper

Application of full-chip level optical proximity correction to memory device with sub-0.10-um design rule and ArF lithography

Hyoung-Soon Yune, Hee-Bom Kim, Wan-Ho Kim, Chang-Nam Ahn, Young-Mog Ham, Ki-Soo Shin

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435724

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Semiconducting wafers, Critical dimension metrology, Model-based design, Data modeling, Reticles, Process modeling, Image processing

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Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.

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