Dr. Dmitry Batuk Profile

Dr. Dmitry Batuk

at imec

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Publications (5)

Proceedings Article | 9 April 2024 Presentation + Paper

Active area patterning for CFET: nanosheet etch

V. Brissonneau, Il Gyo Koo, M. Hosseini, D. Batuk, A. Veloso, G. Mannaert, F. Lazzarino

Proceedings Volume 12958, 1295804 (2024) https://doi.org/10.1117/12.3012322

KEYWORDS: Silicon, Etching, Optical lithography, Nanosheets, Passivation, Semiconducting wafers, Superlattices, Germanium, Oxides, Fin field effect transistors

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Proceedings Article | 1 May 2023 Presentation + Paper

Middle-of-line plasma dry etch challenges for CFET integration

D. Radisic, M. Hosseini, H. Mertens, D. Zhou, V. Vega Gonzalez, S. Wang, B. Chan, D. Batuk, E. Dupuy, Z. Tao, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12499, 1249909 (2023) https://doi.org/10.1117/12.2659095

KEYWORDS: Etching, Optical lithography, Lithography, Plasma etching, Plasma, Dry etching, Critical dimension metrology, Dielectrics

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In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO₂ dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO₂ is developed. This patterning sequence consists of SiO₂ etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)

Proceedings Article | 13 June 2022 Presentation

MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT)

Zheng Tao, Yisuo Li, Waikin Li, Minsoo Kim, Basoene Briggs, Katia Devriendt, Lieve Teugels, Farid Sebai, Christophe Lorant, Clement Porret, Erik Rosseel, Alfonso Sepúlveda Márquez, Nicolas Jourdan, Juergen Boemmels, Jerome Mitard, Philippe Matagne, Efrain Altamirano-Sánchez, Lars-ake Ragnarsson, Anish Dangol, Dmitry Batuk, Gerardo Tadeo Martinez Alanis, Jef Geypen, Kenichi Kanazawa, Testuo Izawa, Masakazu Kakumu, Koji Sakui, Nozomu Harada

Proceedings Volume PC12056, PC120560B (2022) https://doi.org/10.1117/12.2614772

KEYWORDS: Optical lithography, Metals, Etching, Transistors, Atomic layer deposition, Silica, Inspection, Electrodes, Transmission electron microscopy, System on a chip

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Proceedings Article | 25 May 2022 Presentation + Paper

Middle-of-line plasma dry etch challenges for buried power rail integration

Dunja Radisic, A. Veloso, A. Gupta, M. Hosseini, S. Wang, H. Mertens, B. Chan, D. Batuk, G. Martinez, F. Lazzarino, E. Litta, N. Horiguchi

Proceedings Volume 12056, 120560C (2022) https://doi.org/10.1117/12.2616731

KEYWORDS: Etching, Metals, Plasma etching, Optical lithography, Ruthenium, Plasma, Tin, Dielectrics, Dry etching, Molybdenum

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Proceedings Article | 20 March 2020 Presentation + Paper

EUV photoresist reference metrology using TEM tomography

Mark Biedrzycki, Umesh Adiga, Andrew Barnum, Alain Mousa, Jason Arjavac, Rose Marie Haynes, Anne-Laure Charley, Phillipe Leray, Dmitry Batuk

Proceedings Volume 11325, 113251T (2020) https://doi.org/10.1117/12.2552139

KEYWORDS: Transmission electron microscopy, Metrology, Tomography, Image segmentation, Photoresist materials, Atomic force microscopy, Extreme ultraviolet lithography, Semiconducting wafers, Atomic layer deposition, Image filtering

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