Millimeter-wave (mmWave) technology has been employed in many applications due to abundant bandwidth resources and high interference immunity such as telecommunication, automotive radars, and imaging. In this paper, a mmWave transmitter link incorporating PAM4 modulation, resonant tunneling diode (RTD) based oscillator, power amplifier and antenna was proposed. To achieve good linearity and alleviate inter-symbol interference (ISI) caused by channel loss simultaneously, a PAM4 modulation circuit utilizing voltage mode driver and 2-tap pre-emphasis was designed and optimized in TSMC 28 nm CMOS process. The simulation results show that our PAM4 modulation circuit operates properly at 40Gb/s with a differential output swing of up to 800 mVpp under a supply voltage of 0.9 V. The overall power consumption is about 51.3 mW, corresponding to an energy efficiency of 1.28 pJ/bit.
Although millimeter wave (mmWave) wireless communication has the advantages of huge bandwidth, narrow beam and high transmission quality, it also suffers from severe signal attenuation caused by atmospheric absorption and short distance transmission. Therefore, the equalization techniques are normally required in mmWave links. In this paper, a continuous time linear equalization (CTLE) with variable gain for mmWave receiver was designed in IHP 130 nm SiGe BiCMOS process. The CTLE circuit incorporates an active equalizer with negative capacitance converter and a variable gain amplifier (VGA). The negative capacitance structure was used to increase the peaking gain at Nyquist frequency to compensate for the high frequency loss, and the VGA provides an adjustable low frequency gain. The simulation results demonstrate that the tuning capabilities of 12 dB and 5 dB can be respectively achieved for low frequency and high frequency, and the equalization performance is verified for two different channels at 25 Gb/s NRZ data streams.
High speed data links with low jitter and large bandwidth are essential for millimeter-wave (mmWave) communications. In this paper, an analog-domain 4-level pulse amplitude modulation (PAM4) baseband demodulation circuit with low data jitter and ultrahigh data rate was designed. In order to suppress the jitter caused by inter-symbol interference (ISI), a local feedback loop was introduced to extend the bandwidth of threshold slicer. A novel clock and data recovery (CDR) circuit architecture was proposed and optimized to extract the clock pulses with low jitter, thus improving the recovered data quality. A symmetric decoder performs an XOR logic operation to recover the least significant bit (LSB) of PAM4 signal, while the most significant bit (MSB) can be directly obtained from the middle-lane after retiming. The whole demodulation circuit was optimized based on IHP 130nm SiGe BiCMOS technology, and the simulation results indicate that our designed circuit can decode single-channel 50 Gbit/s PAM4 data streams into two 25 Gbit/s NRZ signals, and the peak-to-peak jitter is less than 0.1 UI.
We demonstrate optical bistability in InP/InAlGaAs multi-quantum well(MQW) semiconductor ring lasers(SRL) which
are fabricated by the use of inductively coupled plasma reactive ion etching (ICP-RIE) and can be used in a multi-ring to
achieve all-optical storage. Unlike other international reports, the observed optical bistability has unidirectional regime
started directly from the threshold, skip the first two regimes and greatly reduce the injection current required in
applications. The device described in this article achieves threshold current 56mA which is quite low compared to other
reported devices, and some analysis and experiments on the etching depth have been done.
Silicon photodetector can be integrated with all kinds of Silicon circuits to get monolithic OEIC. A CMOS-process-compatible silicon double-photodetector with structures of P+/N-well and N-well/P-substrate, called PD1 and PD2 respectively, is designed in this paper. The theoretical absolute spectral response and response speed of this double-photodetector are calculated and analyzed. Simulation results in 0.5um standard CMOS process show that the responsivity of the double-photodetector is above 0.2A/W from 400 to 900nm wavelength range without ARC (Anti-Reflection-Coating). Both the effects of the insulated medium layers (SiO2 and Si3N4) in CMOS process and reverse voltage on spectral responsivity are also discussed. When the optical window area is 16.54μmx16.54μm2, the capacitance of PD1 is about 100fF at a reverse voltage of 2.5V. Yet the capacitance of PD2 is almost 1/10 of PD1. With a load-resistor of 50Ω, the response speeds of PD1, PD2 and double-photodetector are 0.628, 2.04 and 2.05ns at 650nm wavelength (corresponding bandwidth about 276MHz, 85MHz and 84.7MHz), respectively. Finally, the co-design of Monolithic OEIC is also discussed. A full CMOS monolithic OEIC for optical-disc signal pickup is designed with this double-detector.
Model is developed for the dc I-V characteristics and microwave small-signal parameters of the InP-based In0.52Al0.28As/In0.65Ga0.35As HEMT’s based on physical principles, and the effect of the extrinsic source and drain resistances has also been included. Using the parameters obtained by this model and the small-signal model of PIN detector, we simulated the transimpedance configurations with an inverter and a cascode input circuit of monolithically integrated PIN-HEMT front-end optical receiver. The results indicate that the cascode input stage can realize a smaller input capacitance than the inverter-type, so it has a wider bandwidth. In order to operate in 2.5Gb/s transmission system, the cascode input stage is applied and the parameters are optimized. The simulations reveal that the transimpedance gain is larger than 63.2dBΩ and the sensitivity is 30dBm when the bit rate is 2.5Gb/s. The results obtained in this paper provide a guideline for the fabrication of PIN-HEMT optical receiver.
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