Mr. Simon Chang Profile

Simon Chang

Group Member of Techn Staff at Texas Instruments Inc

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Publications (11)

Proceedings Article | 16 March 2009 Paper

2D design rule and layout analysis using novel large-area first-principles-based simulation flow incorporating lithographic and stress effects

Steven Prins, James Blatchford, Oluwamuyiwa Olubuyide, Deborah Riley, Simon Chang, Qi-Zhong Hong, T. Kim, Ricardo Borges, Li Lin

Proceedings Volume 7275, 72750C (2009) https://doi.org/10.1117/12.814947

KEYWORDS: Transistors, Data modeling, Lithography, Process modeling, Computer simulations, Logic, 3D modeling, Device simulation, Manufacturing, Resolution enhancement technologies

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As design rules and corresponding logic standard cell layouts continue to shrink node-on-node in accordance with Moore's law, complex 2D interactions, both intra-cell and between cells, become much more prominent. For example, in lithography, lack of scaling of λ/NA implies aggressive use of resolution enhancement techniques to meet logic scaling requirements-resulting in adverse effects such as 'forbidden pitches'-and also implies an increasing range of optical influence relative to cell size. These adverse effects are therefore expected to extend well beyond the cell boundary, leading to lithographic marginalities that occur only when a given cell is placed "in context" with other neighboring cells in a variable design environment [1]. This context dependence is greatly exacerbated by increased use of strain engineering techniques such as SiGe and dual-stress liners (DSL) to enhance transistor performance, both of which also have interaction lengths on the order of microns. The use of these techniques also breaks the formerly straightforward connection between lithographic 'shapes' and end-of-line electrical performance, thus making the formulation of design rules that are robust to process variations and complex 2D interactions more difficult. To address these issues, we have developed a first-principles-based simulation flow to study contextdependent electrical effects in layout, arising not only from lithography, but also from stress and interconnect parasitic effects. This flow is novel in that it can be applied to relatively large layout clips- required for context-dependent analysis-without relying on semi-empirical or 'black-box' models for the fundamental electrical effects. The first-principles-based approach is ideal for understanding contextdependent effects early in the design phase, so that they can be mitigated through restrictive design rules. The lithographic simulations have been discussed elsewhere [1] and will not be presented in detail. The stress calculations are based on a finite-element method, extrapolated to mobility using internal algorithms. While these types of calculations are common in '1D' TCAD space, we have modified them to handle ~10 μm X 10 μm clips in reasonable runtime based on advances in software and optimization of computing resources, structural representations and simulation grids. In this paper, we discuss development and validation of the simulation flow, and show representative results of applying this flow to analyze context-dependent problems in a 32-nm low-power CMOS process. Validation of the flow was accomplished using a well-characterized 40/45-nm CMOS process incorporating both DSL and SiGe. We demonstrate the utility of this approach not only to establishing restrictive design rules for avoiding catastrophic context-dependent effects, but also to flag individual cells and identify cell design practices that exhibit unacceptable levels of context-dependent variability. We further show how understanding the sources of stress variation is vital to appropriately anchoring SPICE models to capture the impact of context-dependent electrical effects. We corroborate these simulations with data from electrical test structures specifically targeted to elucidate these effects.

Proceedings Article | 13 March 2009 Paper

Exploration of complex metal 2D design rules using inverse lithography

Simon Chang, James Blatchford, Steve Prins, Scott Jessen, Thuc Dam, Guangming Xiao, Linyong Pang, Bob Gleason

Proceedings Volume 7275, 72750D (2009) https://doi.org/10.1117/12.814197

KEYWORDS: Metals, Lithography, Photomasks, Optical lithography, Logic, Raster graphics, Resolution enhancement technologies, Computer simulations, Distributed computing, Visualization

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As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Proceedings Article | 17 March 2008 Paper

32nm design rule evaluation through virtual patterning

Scott Jessen, James Blatchford, Steve Prins, Simon Chang, Yiming Gu, Mark Smith, Dale Legband, Chris Sallee

Proceedings Volume 6925, 692518 (2008) https://doi.org/10.1117/12.772685

KEYWORDS: Optical proximity correction, Semiconducting wafers, SRAF, Lithography, Photomasks, Optical lithography, Lithographic illumination, Image segmentation, Manufacturing, Fiber optic illuminators

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Proceedings Article | 17 March 2008 Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Steve Prins, James Blatchford, Simon Chang, Lewis Flanagin, Scott Jessen, Sean O'Brien, Guangming Xiao, Timothy Lin, Thuc Dam, Bob Gleason

Proceedings Volume 6925, 69250E (2008) https://doi.org/10.1117/12.774581

KEYWORDS: Lithography, SRAF, Photomasks, Logic, Optical proximity correction, Lithographic illumination, Printing, Critical dimension metrology, Design for manufacturing, Model-based design

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Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Proceedings Article | 27 March 2007 Paper

Process window and interlayer aware OPC for the 32-nm node

Mark Terry, Gary Zhang, George Lu, Simon Chang, Tom Aton, Robert Soper, Mark Mason, Shane Best, Bill Dostalik, Stefan Hunsche, Jiang Wei Li, Rongchun Zhou, Mu Feng, Jim Burdorf

Proceedings Volume 6520, 65200S (2007) https://doi.org/10.1117/12.714442

KEYWORDS: Optical proximity correction, Metals, Photomasks, Model-based design, SRAF, Tolerancing, Critical dimension metrology, Lithography, Data modeling, Performance modeling

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Proceedings Article | 24 March 2006 Paper

Local CD variation in 65nm node with PSM processes STI topography characterization (I)

Yiming Gu, Simon Chang, Gary Zhang, Karen Kirmse, Duncan Rogers, Leif Olsen, John Lewellen

Proceedings Volume 6152, 615204 (2006) https://doi.org/10.1117/12.655914

KEYWORDS: Critical dimension metrology, Transistors, Semiconducting wafers, Cadmium, Optical proximity correction, Etching, Logic, Line edge roughness, Line width roughness, Scanning electron microscopy

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How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.

Proceedings Article | 24 May 2004 Paper

Scanner overlay mix and match matrix generation: capturing all sources of variation

Stephen DeMoor, Jay Brown, John Robinson, Simon Chang, Colin Tan

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.534359

KEYWORDS: Scanners, Semiconducting wafers, Data modeling, Optical alignment, Overlay metrology, Error analysis, Matrices, Statistical modeling, Phase modulation, Metrology

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Proceedings Article | 2 June 2003 Paper

An improved method to determine optimal alignment sampling layouts

Simon Chang, Stephen DeMoor, Jay Brown, Chris Atkinson, Joshua Roberge

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483662

KEYWORDS: Optical alignment, Overlay metrology, Semiconducting wafers, Chemical elements, Imaging systems, Metrology, Scanners, Data modeling, Roads, Critical dimension metrology

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Proceedings Article | 30 July 2002 Paper

Impact of scanner tilt and defocus on CD uniformity across field

Shangting Detweiler, Simon Chang, Sandra Zheng, Patrick Gagnon, Christopher Baum, Mark Boehm, Jay Brown, Catherine Fruga

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474638

KEYWORDS: Critical dimension metrology, Scanners, Semiconducting wafers, Process control, Scanning electron microscopy, Scatter measurement, Etching, Metrology, Diffractive optical elements, Signal detection

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Proceedings Article | 30 July 2002 Paper

New method to determine optimal photolithography process conditions using scatterometry

Changan Wang, Simon Chang, Mark Boehm

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474578

KEYWORDS: Critical dimension metrology, Lithography, Scanning electron microscopy, Scanners, Scatter measurement, Photoresist processing, Optical lithography, Scatterometry, Monochromatic aberrations, Semiconducting wafers

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Proceedings Article | 20 October 2000 Paper

New event-based methodology to improve photolithography productivity

Simon Chang, Mark Boehm

Proceedings Volume 4226, (2000) https://doi.org/10.1117/12.404851

KEYWORDS: Semiconducting wafers, Optical lithography, Reticles, Optical alignment, Manufacturing, Error analysis, Photoresist processing, Lithography, Data processing, Data analysis

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Showing 5 of 11 publications

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