This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML-HMI) to collect massive data, automated metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch, ASML-Brion) to capture complicated etch behaviors. The model calibration and verification are performed using a combined data from a test and real chip wafer to ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch model, wherein Newron etch model shows significant accuracy improvement in the model calibration (<50% for test patterns and <35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and effectively captured by the Newron etch with a sublayer-aware model form. The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows significant accuracy improvement.
As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.
In advanced DRAM fabrication, wafer alignment is a key enabler to meet on-product overlay performance requirement. Due to the extreme complexity of patterning and integration process involved, it’s becoming a challenge to design alignment marks that can be patterned robustly through process window, meet process integration constraints, withstand large process variation or changes, and provide accurate alignment measurement, during early development. The unique tilted pattern in DRAM fabrication technology poses special challenges during both design and process phase. In this paper, we present a holistic computational approach to design robust alignment marks with ASML’s integrated Design for Control (D4C) and OPC solutions. With this integrated solution, we design a complex set of alignment marks for the entire full flow process from FEOL through BEOL, tailored by each stack of different lithography layers. In mark design stage, marks’ signal and robustness are optimized by D4C simulation, taking into account the design rule and process constraints, while patterning fidelity and process window of these marks is ensured by OPC, subject to the design rule constraints. We demonstrate that the process window (PW) of the resulting alignment marks, especially for the challenging layers with extreme off-axis illuminations and tight design constraints, are significantly improved, while simultaneously accurate and robust alignment measurements are obtained on full loop wafers.
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