Ms. Yi-Han Chang Profile

Yi-Han Chang

PDK Engineer and Researcher at imec

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Profile Summary

I start my career in semiconductor industry since 2013. Writing DRC decks for 14nm technology while working in foundry and cooperated with foundry, design house to adopt and deploy new physical verification tool features while working in EDA tool company. Now, I'm working for imec to maintain and create PDK, and also write Design Rule Manual for different technology nodes.

Publications (6)

Proceedings Article | 12 November 2024 Presentation + Paper

Logic and memory patterning breakthrough using High-NA lithography

V. Blanco Carballo, S. Roy, B. Chowrira, T. Pham, J. Wouters, S. Das, S. Decoster, P. Leray, R. Liu, K. Ronse, G. Vandenberghe, A. Niroomand, P. Foubert, V. Rutigliani, H. Suh, M. Gupta, D. de Simone, M. Dusa, C. Beral, V. Philipsen, V. Wiaux, J. Franke, J. Bekaert, B. Baskaran, W. Gillijns, R. Kim, Y. Sherazi, H. Vats, M. Cupak, C. Chang, Y.-J. Lin, J. Lee, S. Hwang, K. Yang, K. Miyaguchi

Proceedings Volume 13216, 1321604 (2024) https://doi.org/10.1117/12.3047176

KEYWORDS: Metals, Optical lithography, Logic, Semiconducting wafers, Extreme ultraviolet lithography, Etching, Scanning electron microscopy, Lithography, Tin

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Proceedings Article | 10 April 2024 Presentation + Paper

Study of EUV stochastic defect on wafer yield

Yi-Pei Tsai, Chieh-Miao Chang, Yi-Han Chang, Apoorva Oak, Darko Trivkovic, Ryoung-Han Kim

Proceedings Volume 12954, 1295404 (2024) https://doi.org/10.1117/12.3010858

KEYWORDS: Stochastic processes, Extreme ultraviolet, Semiconducting wafers, Data modeling, Photomasks, Critical dimension metrology, Optical lithography, Back end of line, Inspection, Extreme ultraviolet lithography

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Proceedings Article | 10 April 2024 Presentation + Paper

Investigation of die-cost scaling scenarios in future technologies

G. Mirabelli, Y.-P. Tsai, Y.-H. Chang, D. Velenis, R.-H. Kim, J. Myers, L.-Å. Ragnarsson, O. Zografos, G. Hellings

Proceedings Volume 12954, 129540E (2024) https://doi.org/10.1117/12.3010149

KEYWORDS: Semiconductor manufacturing, Back end of line, Logic, Front end of line

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Proceedings Article | 28 April 2023 Poster + Paper

Productivity enhancement study: yield, cost, and turn-around-time modeling for EUV and high NA EUV

Yi-Pei Tsai, Yi-Han Chang, Jane Wang, Darko Trivkovic, Kurt Ronse, Ryoung-Han Kim

Proceedings Volume 12495, 124951U (2023) https://doi.org/10.1117/12.2658866

KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Fin field effect transistors, Optical lithography, Front end of line, Manufacturing, Back end of line, Yield improvement, Extreme ultraviolet lithography

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Proceedings Article | 26 May 2022 Presentation + Paper

Design, patterning, and process integration overview for 2nm node

Syed Muhammad Yasser Sherazi, Yi-Han Chang, Youssef Drissi, Bilal Chehab, Jae Uk Lee, Victor Vega Gonzales, Ryan Ryoung Han Kim

Proceedings Volume 12052, 120520F (2022) https://doi.org/10.1117/12.2615311

KEYWORDS: Metals, Fin field effect transistors, Semiconducting wafers, Optical lithography, 3D imaging standards, Integrated circuits, CMOS devices, Standards development, Field effect transistors, Etching

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Proceedings Article | 26 May 2022 Presentation + Paper

A yield prediction model and cost of ownership for productivity enhancement beyond imec 5nm technology node

Yi-Pei Tsai, Yi-Han Chang, Jane Wang, Darko Trivkovic, Kurt Ronse, Ryoung-Han Kim

Proceedings Volume 12052, 1205203 (2022) https://doi.org/10.1117/12.2617415

KEYWORDS: Extreme ultraviolet, Semiconducting wafers, Photomasks, Manufacturing, Optical lithography, Yield improvement, Front end of line, Semiconductor manufacturing, Performance modeling, Back end of line

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Showing 5 of 6 publications

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