This PDF file contains the front matter associated with SPIE Proceedings Volume 10585 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

The downscaling of features in the semiconductor industry has continuously placed pressure on optics-based measurement methods to yield new solutions for measuring ever-smaller devices. Such measurements are desirable as optics is unique in its combination of high throughput, sensitivity, and non-destructivity. Rigorous electromagnetic modeling has already extended the utility of optical methods such as scatterometry to the measurements of dimensions well-below the conventional diffraction limit. As tolerances decrease with feature size, greater emphasis has been placed upon reducing parametric uncertainties, which can be negatively affected by parametric correlations in the theory-to-experiment fitting process. Parametric uncertainty reductions can be realized though hybrid metrology, the proper statistical treatment of additional quantitative information. As device feature sizes are now pushing towards the sub-5 nm domain, optics-based metrology faces a daunting new challenge. Consider that a 1 nm3 volume of crystalline silicon has just 50 atoms. Although the precise number of atoms across a 5 nm-wide line depends upon the lattice orientation, at these length scales dimensions can be expressed as few as ten atoms in width. At these near-atomic scales, quantized or atomistic effects must be considered especially with respect to the existing framework of electromagnetic scattering simulations and modeling that undergirds quantitative optical measurements. This challenge affects both conventional CMOS devices and also the variety of prospective new structures, such as “gate all around” transistors, nanowire based devices, and tunnel field effect transistors. Accurate determination of the real and imaginary dielectric constants e_1 and e_2 prove to be key to the extensibility of Maxwell’s Equations to these low dimensional structures. Several potential solutions to aspects of this measurement challenge are found in the literature, ranging from empirical determinations assuming an effective media [1] to density functional theory calculations of the electronic properties and the bulk dielectric tensors [2]. We will build upon such solutions from the literature and discuss additional alternatives such as the hybridization of multiple measurements or techniques, shorter measurement wavelengths, and enhanced hardware platforms. Figure 1 (see attachment) shows preliminary work underway in this effort. A Tauc-Lorentz fitting of scatterometry parameters (Delta) and (Psi) yields the thickness-dependent e_1 and e_2 for our initial sample set. This work will address not just the implications for thin films (i.e. two-dimensional structures) but also outline the challenges for one-dimensional and zero-dimensional structures as well. Figure 1. (a) Schematic of an initial sample set for experimentally demonstrating changes in the dielectric constant as a function of layer thickness. Samples were prepared using atomic layer deposition. (b) Dielectric constants e_1, e_2 for the sample set as function of photon energy. Permittivity decreases as a function of decreasing HfO2 thickness. [1] P. Ebersbach, et al., “Monitoring of ion implantation in microelectronics production environment using multi-channel reflectometry,” Proc. SPIE 9778, 977812 (2016). [2] P. Pusching and C. Anbrosch-Draxl, “Atomistic Modeling of Optical Properties of Thin Films,” Adv. Eng. Mat. 8, 1151-1155 (2006).

Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration flow (2). This in turn allows to extend the usage of existing process and metrology platforms, and reduce the cost of shifting to a new technology. Even though the integration changes seem limited, it springs many new obstacle for fab metrology. New parameters of interest take place, and the metrology capability needs to reach higher performance, and develop new solution methods (3,4). The current paper will focus on one of the new rising metrology challenges, which exist at the nanowire release process step. The nanowire release step, a SiGe dummy layer is being removed by dry etching, to leave behind the active Silicon nanowires, for nfet device. A detailed metrology of these nanowire profile and thickness is required to verify the device can perform to the expected specifications. To examine the scatterometry performance at this application, a specific design of experiment was set, at multiple process step. at fin formation we begin with split condition, on the silicon-silicon germanium (Si-SiGe) multi layer deposition, where SiGe , are being varied between wafers, by increasing the SiGe layer thickness, thus different amount of SiGe material will be released (figure 1a). Scatterometry and X-ray reflectivity (XRR) are verifying this split condition (figure 1b). We continue with additional split condition for the fin reveal, allowing the lower SiGe layer to be more or less revealed to the SiGe release etching step (figure 2a). To confirm the fin height for the different splits condition we use atomic force microscope (AFM), and scatterometry (figure 2b). the last process DoE we report is the etching method in which the SiGe is released. The two etch methods, we address in this paper, provides different nanowire profile (figure 3), a circular or rectangular shapes, respectively. The last part of this paper will highlight how scatterometry nanowire profile accuracy, at the SiGe release step, is improved by incorporating the complete GAA steps scatterometry solutions, and the combination of Transmission electron microscopy (TEM) rich sampling.

In this paper, we report on Muller Matrix (MM) based scatterometry (aka. optical critical dimension or OCD) simulation strategies for two sub-7nm fin structures: one with a SixGe1-x/Si/SixGe1-x/Si/SixGe1-x/Si nanosheet structure and its comparison with a hypothetical Si-only fin structure of similar dimensions at sub-7nm semiconductor technology nodes. Si-fins are providing the performance improvements necessary for the transistors used in current generation integrated circuits. Development of sub-7nm technology nodes requires further performance improvements including advanced structures including new materials. This demand for improved performance has created the need for new fabrication processes such as extreme ultraviolet lithography, self-aligned quadruple patterning etc., along with new metrology challenges for adequately monitoring the semiconductor process control during fabrication of these advanced nanostructures.1 New materials and structures, such as, Si/Si1-xGex (0≤x≤1) stacked nanosheet structures have recently been developed as one of the potential replacement for Si-based FinFETs.2,3 We have simulated two fin structures: one with Si-fins and another with 3 alternating stacks of Si1-xGex/Si (x=0.3). We have used Rigorous Coupled Wave Approximation (RCWA) to simulate OCD spectra for 0° – 360° azimuthal angles in 10° steps by keeping the fin pitch fixed at 24nm while systematically changing (1) the fin critical dimension (CD) from 5.0–7.5nm in 0.5nm steps, (2) thickness of the Si and Si1-xGex (x=0.3) nanosheets (NST) from 8.0–1.5nm in 0.5nm steps, (3) the fin bending angle (FBA) from 0°–2.5° in 0.5° steps, and (4) the undercut angle (ED) of the Si1-xGex NSTs from 0°–10° in 2° steps. Difference in etch-rate of Si and Ge could give rise to non-zero ED during NST formation. Both the fin structures possess mirror symmetry about two orthogonal planes perpendicular to the substrate and with one of the planes along the fin long-axis. For angles 0°, 90°, 180°, and 270°, this mirror symmetry leads to absence of the cross-polarization terms in the simulated OCD spectra such that off-diagonal MM elements are zero over the simulated wavelength range. The broken mirror symmetry in other azimuthal angles leads to cross-polarization of the electrical field vectors which is seen in the off-diagonal MM elements becoming non-zero. Additionally, the off-diagonal MM elements show increased sensitivity and reduced correlation between the parameters under study which leads to a powerful metrology means for studying the critical fin-parameters for fast and reliable semiconductor process control in sub 7-nm technology nodes. All the non-zero MM-elements are found to be sensitive to changes in CD and NST with the off-diagonal elements showing greater sensitivity to the changes. At azimuthal angles <15°, MM23, MM31, and MM34 are highly sensitive to changes in etch undercut and fin bending angle defects. References: [1] D. Dixit et al., “Advanced applications of scatterometry based optical metrology,” Proc SPIE 10145, 101451H (2017). [2] N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” VLSI Technol. 2017 Symp., T230–T231, IEEE (2017). [3] R. Muthinti et al., “Advanced in-line optical metrology of sub-10nm structures for gate all around devices (GAA),” Proc SPIE 9778, 977810 (2016).

With these proceedings we present μ-diffraction-based overlay (μDBO) targets that are well below the currently supported minimum size of 10×10 μm² . We have been capable of measuring overlay targets as small as 4×4 μm² with our latest generation YieldStar system. Furthermore we find an excellent precision (TMU < 0.33 nm for 6 × 6 μm² ) without any compromise on throughput (MAM time < 60 ms). At last a study that compares four generations of YieldStar systems show clearly that the latest generation YieldStar systems is much better capable of reading small overlay targets such that the performance of a 16 × 16 μm² on an early generation YieldStar 2nd-gen is comparable to that of a 8 × 8 μm² on the latest YieldStar 5th-gen. This work enables a smaller metrology footprint, more placement flexibility and in-die overlay metrology solutions.

In this paper, we propose a technique called time-varying frequency scanning (TVFS) to meet the challenges in killer defect inspection. The proposed technique enables the dynamic monitoring of defects by checking the hopping in the instantaneous frequency data and the classification of defect types by comparing the difference in frequencies. The TVFS technique utilizes the bidimensional empirical mode decomposition (BEMD) method to separate the defect information from the sea of system errors. This significantly improve the signal-to-noise ratio (SNR) and moreover, it potentially enables reference-free defect inspection.

In this paper, we present a method for accurate EUV mask inspection of arbitrarily shaped absorber patterns using lensless imaging methods. With our reflective-mode EUV mask scanning lensless imaging microscope (RESCAN), we have imaged a mask with programmed defects and present here the computed defect map for both die-to-die and die-to-database pattern inspection. The signal-to-noise ratio in both cases was high enough to clearly isolate the defect from the structures (~13 for die-to-die and ~7 for die-to-database inspection). To reach the high-throughput required by industry, we implemented an extended ptychographic algorithm that allows for continuous scanning of the sample and subsequent deconvolution of the distortions in the incident illumination that are due to the fast stage movement. We will show how this algorithm was implemented on a multi-GPU platform for maximum performance that will eventually allow us to reach the final goal of 7 hours scan time for a full mask.

In recent publications, our group has presented simulation studies that investigated the applicability of five ultraviolet inspection wavelengths for defect detection using a signal-to-noise ratio (SNR) based defect metric. All computations were performed using our in-house finite-difference time-domain (FDTD) Maxwell’s equations solver. Initial simulations contained no perturbations except for the defect. In the absence of noise, the defects are readily apparent, and we therefore added Poisson noise both to the defect and no-defect simulated images that yield the differential image. For these noisy differential images, signal and noise were separated to calculate the SNR with two additional variables: an area threshold A_min and a noise threshold σ. A wavelength dependent A_min (λ) that scaled linearly with wavelength was required to enable comparison across all five wavelengths. All types of defects were best resolved using an inspection wavelength of λ=47 nm assuming ideal conditions (i.e. no variation in numerical aperture or source intensity as a function of wavelength.) In this work, we add line edge roughness as “wafer noise” on both defect and no-defect geometries to test this SNR approach in a more realistic way. Various permutations of defect types, polarizations, illumination angles, focal planes and wavelengths affect the differential images produced differently. For every combination of the above mentioned experimental setups we individually maximize the SNR as a function of A_min and σ to improve defect detection, and trends across wavelengths are assessed. Finally, we present an alternative approach to the defect detection that is based on a neural network. We address questions of feature selection and its relation to the previous used SNR approach.

A methodology to evaluate the electrical contact between nanowire (NW) and source/drain (SD) in NW FETs was investigated with SEM voltage contrast (VC). The electrical defects were robustly detected by VC. The validity of the inspection result was verified by TEM physical observations. Moreover, estimation of the parasitic resistance and capacitance was achieved from the quantitative analysis of VC images which were acquired with different scan conditions of electron beam (EB). A model considering the dynamics of EB-induce charging was proposed to calculate the VC. The resistance and capacitance can be determined by comparing the model-based VC with experimentally obtained VC. Quantitative estimation of resistance and capacitance would be valuable not only for more accurate inspection, but also for identification of the defect point.

Through-focus optical microscopy (TSOM) with nanometer-scale lateral and vertical sensitivity levels matching those of scanning electron microscopy has been demonstrated to be useful both for 3D inspections and metrology assessments. In 2014, funded by two private companies (Nextin/Samsung Electronics) and the Korea Evaluation Institute of Industrial Technology (KEIT), a research team from four universities in South Korea set out to investigate core technologies for developing in-line TSOM inspection and metrology tools, with the respective teams focusing on optics implementation, defect inspection, computer simulation and high-speed metrology matching. We initially confirmed the reported validity of the TSOM operation through a computer simulation, after which we implemented the TSOM operation by throughfocus scanning of existing UV (355nm) and IR (800nm) inspection tools. These tools have an identical sampling distance of 150 nm but have different resolving distances (310 and 810 nm, respectively). We initially experienced some improvement in the defect inspection sensitivity level over TSV (through-silicon via) samples with ~ 6.6 μm diameters. However, during the experiment, we noted sensitivity and instability issues when attempting to acquire TSOM images. As TSOM 3D information is indirectly extracted by differentiating a target TSOM image from reference TSOM images, any instability or mismatch in imaging conditions can result in measurement errors. As a remedy to such a situation, we proposed the application of adaptive optics to the TSOM operation and developed a closed-loop system with a tip/tilt mirror and a Shack-Hartmann sensor on an optical bench. We were able to keep the plane position within in RMS 0.4 pixel by actively compensating for any position instability which arose during the TSOM scanning process along the optical axis. Currently, we are also developing another TSOM tool with a deformable mirror instead of a tip/tilt mirror, in which case we will not require any mechanical scanning.

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

LER (Line Edge Roughness) and LWR (Line Width Roughness) of the semiconductor device are an important evaluation scale of the performance of the device. Conventionally, LER and LWR is evaluated from CD-SEM (Critical Dimension Scanning Electron Microscope) images. However, CD-SEM measurement has a problem that high frequency random noise is large, and resolution is not sufficiently high. For random noise of CD-SEM measurement, some techniques are proposed. In these methods, it is necessary to set parameters for model and processing, and it is necessary to verify the correctness of these parameters using reference metrology. We have already proposed a novel reference metrology using FIB (Focused Ion Beam) process and planar-TEM (Transmission Electron Microscope) method. In this study, we applied the proposed method to three new samples such as SAQP (Self-Aligned Quadruple Patterning) FinFET device, EUV (Extreme Ultraviolet Lithography) conventional resist, and EUV new material resist. LWR and PSD (Power Spectral Density) of LWR are calculated from the edge positions on planar-TEM images. We confirmed that LWR and PSD of LWR can be measured with high accuracy and evaluated the difference by the proposed method. Furthermore, from comparisons with PSD of the same sample by CD-SEM, the validity of measurement of PSD and LWR by CD-SEM can be verified.

Nowadays, roughness control presents a huge challenge for the lithography step. For advanced nodes, this morphological aspect reaches the same order of magnitude than the Critical Dimension. Hence, the control of roughness needs an adapted metrology. In this study, specific samples with designed roughness have been manufactured using e-beam lithography. These samples have been characterized with three different methodologies: CD-SEM, OCD and SAXS. The main goal of the project is to compare the capability of each of these techniques in terms of reliability, type of information obtained, time to obtain the measurements and level of maturity for the industry.

Line-edge roughness (LER) and linewidth roughness (LWR) in semiconductor processing are best characterized by the roughness power spectral density (PSD), or similar measures of roughness frequency and correlation. The PSD is generally thought to be described well by three parameters: standard deviation, correlation length, and PSD(0), the extrapolated zero frequency PSD. The next step toward enabling these metrics for pertinent industrial use is to understand how real metrology errors interact with these metrics and what should be optimized on the critical dimension scanning electron microscopy (CD-SEM) to improve error budgets. In this work, both images from multiple models of commercially-available CD-SEMs and from JMONSEL simulation of modeled roughened lines are used to better understand how various SEM algorithm choices, parameters, beam size/shape, and pixel size/scanning scheme influence SEM line edge uncertainty. Furthermore, how these errors interact with the above-listed PSD metrics will be explored, imparting knowledge for optimizing LER PSD measurement with minimized error. The Analytical Linescan Model (ALM) is a physics-based semi-empirical expression that predicts a SEM linescan given a specified wafer geometry. It can be calibrated to rigorous Monte Carlo simulations. Unlike Monte Carlo simulations, however, the analytical form of the ALM makes computational times very small. Inverting the ALM to produce an inverse linescan model allows wafer geometries to be estimated based on experimental linescan measurements. Thus, an inverse linescan model can be used as an edge detection algorithm for dimensional measurement directly from CD-SEM generated images. Here, an inverse linescan model will be tested as a potential CD, LER, and LWR measurement algorithm and compared to other conventional measurement algorithms.

Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, PSD prediction, sampling strategy, and noise mitigation, and general guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as wave-matching method are shown effective for robustly detecting edges from low SNR images, while conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. Advanced PSD prediction method such as multi-taper method is effective in suppressing sampling noise within a line edge to analyze, while number of lines is still required for suppressing line to line variation. Two types of SEM noise mitigation methods, "apparent noise floor" subtraction method and LER-noise decomposition using regression analysis are verified to successfully mitigate SEM noise from PSD curves. These results are extended to LCDU measurement to clarify the impact of SEM noise and sampling noise on LCDU.

This paper will provide an update to previous works [2][4][9] to our view of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry, concentrating on logic technology for foundries. First, we will review of the needs of patterned defect, critical dimensional (CD/3D), overlay and films metrology, and present the extensive list of applications for which metrology solutions are needed. We will then update the industry’s progress towards addressing gating technical limits of the most important of these metrology solutions, highlighting key metrology technology gaps requiring industry attention and investment.

CD-SEMs are an indispensable part of semiconductor manufacturing. Extending their functionality beyond routine work on CD metrology of a layer is highly desirable. The etch process greatly depends on CDs and the pitch of a pattern. Through pitch patterns consisting of two layers, each with different CDs and side wall angles, are widely used to develop and characterize etch processes. TEMs are widely used to measure these values for each layer. This is a time consuming and expensive process, and the feedback time to process development is long. It would be highly desirable to develop metrology for two layers, including their side wall angles, using top down SEM images in order to reduce cost and provide a fast feedback to process development and characterization. A technique was developed to measure top and bottom CDs of each layer, as well as side wall angles of the layers using SEM images. The model based myCD software was used as the basis for this development. Hundreds of SEM images were taken at multiple test pattern areas with variable pitch and dimensions. The extracted values included top and bottom CDs of the top layer, top and bottom CDs of the bottom layer, as well as side wall angles of both layers. The pitch was also extracted for verification. The results of CDs and SWA were very consistent. The verification was done in two ways: a) by comparing myCD results to results from corresponding TEM images; and b) by analyzing the noise of the measured data. It is believed that the variation of CDs and SWAs on the through pitch pattern was consistent with the designed pattern layout and their variation from the design due to process variation should be smooth. Both verifications confirmed excellent results of metrology. In particular, the repeatability of SWA measurements from top down images was found to be 0.4 degrees, a 3-sigma variation. There is no other method to our knowledge to measure SWA from top down images.

With increasingly 3D devices becoming the norm, there is a growing need in the semiconductor industry and in materials science for high spatial resolution, non-destructive metrology techniques capable of determining depth-dependent composition information on devices. We present a solution to this problem using ptychographic coherent diffractive imaging (CDI) implemented using a commercially available, tabletop 13 nm source. We present the design, simulations, and preliminary results from our new complex EUV imaging reflectometer, which uses coherent 13 nm light produced by tabletop high harmonic generation. This tool is capable of determining spatially-resolved composition vs. depth profiles for samples by recording ptychographic images at multiple incidence angles. By harnessing phase measurements, we can locally and nondestructively determine quantities such as device and thin film layer thicknesses, surface roughness, interface quality, and dopant concentration profiles. Using this advanced imaging reflectometer, we can quantitatively characterize materials-sciencerelevant and industry-relevant nanostructures for a wide variety of applications, spanning from defect and overlay metrology to the development and optimization of nano-enhanced thermoelectric or spintronic devices.

Using a tabletop coherent extreme ultraviolet source, we extend current nanoscale metrology capabilities with applications spanning from new models of nanoscale transport and materials, to nanoscale device fabrication. We measure the ultrafast dynamics of acoustic waves in materials; by analyzing the material’s response, we can extract elastic properties of films as thin as 11nm. We extend this capability to a spatially resolved imaging modality by using coherent diffractive imaging to image the acoustic waves in nanostructures as they propagate. This will allow for spatially resolved characterization of the elastic properties of non-isotropic materials.

Image Based Overlay (IBO) measurement is one of the most common techniques used in Integrated Circuit (IC) manufacturing to extract the overlay error values. The overlay error is measured using dedicated overlay targets which are optimized to increase the accuracy and the resolution, but these features are much larger than the IC feature size. IBO measurements are realized on the dedicated targets instead of product features, because the current overlay metrology solutions, mainly based on optics, cannot provide sufficient resolution on product features. However, considering the fact that the overlay error tolerance is approaching 2 nm, the overlay error measurement on product features becomes a need for the industry. For sub-nanometer resolution metrology, Scanning Probe Microscopy (SPM) is widely used, though at the cost of very low throughput. The semiconductor industry is interested in non-destructive imaging of buried structures under one or more layers for the application of overlay and wafer alignment, specifically through optically opaque media. Recently an SPM technique has been developed for imaging subsurface features which can be potentially considered as a solution for overlay metrology. In this paper we present the use of Subsurface Ultrasonic Resonance Force Microscopy (SSURFM) used for IBO measurement. We used SSURFM for imaging the most commonly used overlay targets on a silicon substrate and photoresist. As a proof of concept we have imaged surface and subsurface structures simultaneously. The surface and subsurface features of the overlay targets are fabricated with programmed overlay errors of ±40 nm, ±20 nm, and 0 nm. The top layer thickness changes between 30 nm and 80 nm. Using SSURFM the surface and subsurface features were successfully imaged and the overlay errors were extracted, via a rudimentary image processing algorithm. The measurement results are in agreement with the nominal values of the programmed overlay errors.

The advance of the semiconductor industry requires new metrology methods, which can deal with smaller and more complex nanostructures. Particularly for inline metrology a rapid, sensitive and non destructive method is needed. Small angle X-ray scattering under grazing incidence has already been investigated for this application and delivers significant statistical information which tracks the profile parameters as well as their variations, i.e. roughness. However, it suffers from the elongated footprint at the sample. The advantage of EUV radiation, with its longer wavelengths, is that larger incidence angles can be used, resulting in a significant reduction of the beam footprint. Targets with field sizes of 100 μm and smaller are accessible with our experimental set-up. We present a new experimental tool for the measurement of small structures based on the capabilities of soft X-ray and EUV scatterometry at the PTB soft X-ray beamline at the electron storage ring BESSY II. PTB’s soft X-ray radiometry beamline uses a plane grating monochromator, which covers the spectral range from 0.7 nm to 25 nm and was especially designed to provide highly collimated radiation. An area detector covers the scattered radiation from a grazing exit angle up to an angle of 30° above the sample horizon and the fluorescence emission can be detected with an energy dispersive X-ray silicon drift detector. In addition, the sample can be rotated and linearly moved in vacuum. This new set-up will be used to explore the capabilities of EUV-scatterometry for the characterization of nanometre-sized structures.

In this paper, we present an electromagnetic full-wave modeling framework, as a support EM tool providing data sets for X-ray ptychographic imaging. Modeling the entire scattering problem with Finite Element Method (FEM) tools is, in fact, a prohibitive task, because of the large area illuminated by the beam (due to the poor focusing power at these wavelengths) and the very small features to be imaged. To overcome this problem, the spectrum of the illumination beam is decomposed into a discrete set of plane waves. This allows reducing the electromagnetic modeling volume to the one enclosing the area to be imaged. The total scattered field is reconstructed by superimposing the solutions for each plane wave illumination.

Nondestructive subsurface nanoimaging through optically opaque media is considered to be extremely challenging and is essential for several semiconductor metrology applications including overlay and alignment and buried void and defect characterization. The current key challenge in overlay and alignment is the measurement of targets that are covered by optically opaque layers. Moreover, with the device dimensions moving to the smaller nodes and the issue of the so-called loading effect causing offsets between between targets and product features, it is increasingly desirable to perform alignment and overlay on product features or so-called on-cell overlay, which requires higher lateral resolution than optical methods can provide. Our recently developed technique known as SubSurface Ultrasonic Resonance Force Microscopy (SSURFM) has shown the capability for high-resolution imaging of structures below a surface based on (visco-)elasticity of the constituent materials and as such is a promising technique to perform overlay and alignment with high resolution in upcoming production nodes. In this paper, we describe the developed SSURFM technique and the experimental results on imaging buried features through various layers and the ability to detect objects with resolution below 10 nm. In summary, the experimental results show that the SSURFM is a potential solution for on-cell overlay and alignment as well as detecting buried defects or voids and generally metrology through optically opaque layers.

In overlay (OVL) metrology the quality of measurements and the resulting reported values depend heavily on the measurement setup used. For example, in scatterometry OVL (SCOL) metrology a specific target may be measured with multiple illumination setups, including several apodization options, two possible laser polarizations, and multiple possible laser wavelengths. Not all possible setups are suitable for the metrology method as different setups can yield significantly different performance in terms of the accuracy and robustness of the reported OVL values. Finding an optimal measurement setup requires great flexibility in measurement, to allow for high-resolution landscape mapping (mapping the dependence of OVL, other metrics, and details of pupil images on measurement setup). This can then be followed by a method for analyzing the landscape and selecting an accurate and robust measurement setup. The selection of an optimal measurement setup is complicated by the sensitivity of metrology to variations in the fabrication process (process variations) such as variations in layer thickness or in the properties of target symmetry. The metrology landscape changes with process variations and maintaining optimal performance might require continuous adjustments of the measurement setup. Here we present a method for the selection and adjustment of an optimal measurement setup. First, the landscape is measured and analyzed to calculate theory-based accurate OVL values as well as quality metrics which depend on details of the pupil image. These OVL values and metrics are then used as an internal ruler (“self-reference”), effectively eliminating the need for an external reference such as CD-SEM. Finally, an optimal measurement setup is selected by choosing a setup which yields the same OVL values as the self-reference and is also robust to small changes in the landscape. We present measurements which show how a SCOL landscape changes within wafer, wafer to wafer, and lot to lot with intentionally designed process variations between. In this case the process variations cause large shifts in the SCOL landscape and it is not possible to find a common optimal measurement setup for all wafers. To deal with such process variations we adjust the measurement setup as needed. Initially an optimal setup is chosen based on the first wafer. For subsequent wafers the process stability is continuously monitored. Once large process variations are detected the landscape information is used for selecting a new measurement setup, thereby maintaining optimal accuracy and robustness. Methods described in this work are enabled by the ATL (Accurate Tunable Laser) scatterometry-based overlay metrology system.

Ever increasing need for tighter on-product overlay (OPO), as well as enhanced accuracy in overlay metrology and methodology, is driving semiconductor industry’s technologists to innovate new approaches to OPO measurements. In case of High Volume Manufacturing (HVM) fabs, it is often critical to strive for both accuracy and robustness. Robustness, in particular, can be challenging in metrology since overlay targets can be impacted by proximity of other structures next to the overlay target (asymmetric effects), as well as symmetric stack changes such as photoresist height variations. Both symmetric and asymmetric contributors have impact on robustness. Furthermore, tweaking or optimizing wafer processing parameters for maximum yield may have an adverse effect on physical target integrity. As a result, measuring and monitoring physical changes or process abnormalities/artefacts in terms of new Key Performance Indicators (KPIs) is crucial for the end goal of minimizing true in-die overlay of the integrated circuits (ICs). IC manufacturing fabs often relied on CD-SEM in the past to capture true in-die overlay. Due to destructive and intrusive nature of CD-SEMs on certain materials, it’s desirable to characterize asymmetry effects for overlay targets via inline KPIs utilizing YieldStar (YS) metrology tools. These KPIs can also be integrated as part of (μDBO) target evaluation and selection for final recipe flow. In this publication, the Holistic Metrology Qualification (HMQ) flow was extended to account for process induced (asymmetric) effects such as Grating Imbalance (GI) and Bottom Grating Asymmetry (BGA). Local GI typically contributes to the intrafield OPO whereas BGA typically impacts the interfield OPO, predominantly at the wafer edge. Stack height variations highly impact overlay metrology accuracy, in particular in case of multi-layer LithoEtch Litho-Etch (LELE) overlay control scheme. Introducing a GI impact on overlay (in nm) KPI check quantifies the grating imbalance impact on overlay, whereas optimizing for accuracy using self-reference captures the bottom grating asymmetry effect. Measuring BGA after each process step before exposure of the top grating helps to identify which specific step introduces the asymmetry in the bottom grating. By evaluating this set of KPI's to a BEOL LELE overlay scheme, we can enhance robustness of recipe selection and target selection. Furthermore, these KPIs can be utilized to highlight process and equipment abnormalities. In this work, we also quantified OPO results with a self-contained methodology called Triangle Method. This method can be utilized for LELE layers with a common target and reference. This allows validating general μDBO accuracy, hence reducing the need for CD-SEM verification.

One of the metrology challenges for massively parallel electron beams is to verify that all the beams that are used perform within specification. The Mapper FLX-1200 platform exposes fields horizontally segmented in 2.2 μm-wide stripes. This yields two parameters of interest: overlay is the registration error with respect to a previous layer, and stitching is the registration error between the stripes. This paper presents five novel overlay targets and one novel stitching target tailored for Mapper’s needs and measured on KLA-Tencor Archer 600 image based overlay (IBO) platform. The targets have been screened by exposure of a variable shaped electron beam lithography machine (Vistec VSB 3054 DW) on two different stacks: resist-to-resist and resist-to-etched silicon, both as a trilayer stack. These marks attain a total measurement uncertainty (TMU) down to 0.3 nm and move-and-measure (MAM) time down to 0.3 seconds for both stacks. The stitching targets have an effective TMU of 0.4 nm and a MAM time of 0.75 seconds. In a follow up experiment, the two best performing overlay targets have been incorporated in an exposure by a Mapper FLX-1200. With the new stack a TMU of 0.3 nm and MAM time of 0.35 s have been attained. For 107 out of 140 selected stripes the slope was constant within 2.5%, the offset smaller than 0.5 nm and correlation coefficient R² > 0.98.

This paper demonstrates the improvement using the YieldStar S-1250D small spot, high-NA, after-etch overlay in-device measurements in a DRAM HVM environment. It will be demonstrated that In-device metrology (IDM) captures after-etch device fingerprints more accurately compared to the industry-standard CDSEM. Also, IDM measurements (acquiring both CD and overlay) can be executed significantly faster increasing the wafer sampling density that is possible within a realistic metrology budget. The improvements to both speed and accuracy open the possibility of extended modeling and correction capabilities for control. The proof-book data of this paper shows a 36% improvement of device overlay after switching to control in a DRAM HVM environment using indevice metrology.

Accuracy of patterning impacts yield, IC performance and technology time to market. Accuracy of patterning relies on optical proximity correction (OPC) models built using CD-SEM inputs and intra die critical dimension (CD) control based on CD-SEM. Sub-nanometer measurement uncertainty (MU) of CD-SEM is required for current technologies. Reported design and process related bias variation of CD-SEM is in the range of several nanometers. Reference metrology and numerical modeling are used to correct SEM. Both methods are slow to be used for real time bias correction. We report on real time CD-SEM bias correction using empirical models based on reference metrology (RM) data. Significant amount of currently untapped information (sidewall angle, corner rounding, etc.) is obtainable from SEM waveforms. Using additional RM information provided for specific technology (design rules, materials, processes) CD extraction algorithms can be pre-built and then used in real time for accurate CD extraction from regular CD-SEM images. The art and challenge of SEM modeling is in finding robust correlation between SEM waveform features and bias of CD-SEM as well as in minimizing RM inputs needed to create accurate (within the design and process space) model. The new approach was applied to improve CD-SEM accuracy of 45 nm GATE and 32 nm MET1 OPC 1D models. In both cases MU of the state of the art CD-SEM has been improved by 3x and reduced to a nanometer level. Similar approach can be applied to 2D (end of line, contours, etc.) and 3D (sidewall angle, corner rounding, etc.) cases.

In recent years, the combination of device scaling, complex 3D device architecture and tightening process tolerances have strained the capabilities of optical metrology tools to meet process needs. Two main categories of approaches have been taken to address the evolving process needs. In the first category, new hardware configurations are developed to provide more spectral sensitivity. Most of this category of work will enable next generation optical metrology tools to try to maintain pace with next generation process needs. In the second category, new innovative algorithms have been pursued to increase the value of the existing measurement signal. These algorithms aim to boost sensitivity to the measurement parameter of interest, while reducing the impact of other factors that contribute to signal variability but are not influenced by the process of interest. This paper will evaluate the suitability of machine learning to address high volume manufacturing metrology requirements in both front end of line (FEOL) and back end of line (BEOL) sectors from advanced technology nodes. In the FEOL sector, initial feasibility has been demonstrated to predict the fin CD values from an inline measurement using machine learning. In this study, OCD spectra were acquired after an etch process that occurs earlier in the process flow than where the inline CD is measured. The fin hard mask etch process is known to impact the downstream inline CD value. Figure 1 shows the correlation of predicted CD vs downstream inline CD measurement obtained after the training of the machine learning algorithm. For BEOL, machine learning is shown to provide an additional source of information in prediction of electrical resistance from structures that are not compatible for direct copper height measurement. Figure 2 compares the trench height correlation to electrical resistance (Rs) and the correlation of predicted Rs to the e-test Rs value for a far back end of line (FBEOL) metallization level across 3 products. In the case of product C, it is found that the predicted Rs correlation to the e-test value is significantly improved utilizing spectra acquired at the e-test structure. This paper will explore the considerations required to enable use of machine learning derived metrology output to enable improved process monitoring and control. Further results from the FEOL and BEOL sectors will be presented, together with further discussion on future proliferation of machine learning based metrology solutions in high volume manufacturing.

A key sensor element in a Hard Disk Drive (HDD) is the read-write head device. The device is complex 3D shape and its fabrication requires over thousand process steps with many of them being various types of image inspection and critical dimension (CD) metrology steps. In order to have high yield of devices across a wafer, very tight inspection and metrology specifications are implemented. Many images are collected on a wafer and inspected for various types of defects and in CD metrology the quality of image impacts the CD measurements. Metrology noise need to be minimized in CD metrology to get better estimate of the process related variations for implementing robust process controls. Though there are specialized tools available for defect inspection and review allowing classification and statistics. However, due to unavailability of such advanced tools or other reasons, many times images need to be manually inspected. SEM Image inspection and CD-SEM metrology tools are different tools differing in software as well. SEM Image inspection and CD-SEM metrology tools are separate tools differing in software and purpose. There have been cases where a significant numbers of CD-SEM images are blurred or have some artefact and there is a need for image inspection along with the CD measurement. Tool may not report a practical metric highlighting the quality of image. Not filtering CD from these blurred images will add metrology noise to the CD measurement. An image classifier can be helpful here for filtering such data. This paper presents the use of artificial intelligence in classifying the SEM images. Deep machine learning is used to train a neural network which is then used to classify the new images as blurred and not blurred. Figure 1 shows the image blur artefact and contingency table of classification results from the trained deep neural network. Prediction accuracy of 94.9 % was achieved in the first model. Paper covers other such applications of the deep neural network in image classification for inspection, review and metrology.

Multi-channel gate all around (GAA) semiconductor devices require measurements of more target parameters than FinFET devices, due in part to the increased complexity of the different structures needed to fabricate nanosheet devices. In some cases, multiple measurement techniques are required to be used in a hybrid-metrology technique in order to properly extract the necessary information. Optical scatterometry (optical critical dimension, or OCD) is an inline metrology technique which is used to measure the geometrical profile of the structure, but it may not ordinarily be sensitive to very small residues. X-ray based metrologies, such as x-ray fluorescence (XRF) can be used to identify which materials are present in the structure, but are not able to measure profile information for complex 3D structures. This paper reviews a critical etch process step, where neither OCD nor XRF can extract all of the necessary information about the structure on their own, but, when hybridized, are able to provide enough information to solve the application. In GAA structures, the nanosheets are formed from alternating layers of thin SiGe and Si layers which are deposited on a bulk Si substrate. To form the nFET channel, the SiGe must be removed. However, in some cases, there is still remaining SiGe residue on the surface of the Si nanosheets, present in small amounts that are difficult to measure with conventional OCD. Additionally, it is desirable to know at which level of the stacked nanosheets the residue is present. In order to properly characterize the amount of SiGe remaining, data from both OCD and XRF are used. By measuring before and after the etch, the XRF can calculate the percentage of SiGe that is remaining after the etch. This percentage can be used as a constraint in the OCD model to allow the OCD to accurately measure the amount of SiGe, and to enable the OCD model to identify the location of the residue.

As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect. Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.

Monitoring of pattern roughness for advanced technology nodes is crucial as this roughness can adversely affect device yield and degrade device performance. The main industry work horse for in-line roughness measurements is the CD-SEM, however, today no adequate reference metrology tools exist that allow to evaluate its roughness measurement sensitivity and precision. To bridge this gap, in this work the roughness measurement capabilities of different analytical techniques are investigated. Different metrology methods are used to evaluate roughness on a same set of samples and results are compared and used in a holistic approach to better characterize and quantify the measured pattern roughness. To facilitate the correlation between the various metrology techniques and the evaluation of CD-SEM sensitivity, an effective approach is to induce pattern roughness in a controlled way by adding well defined levels of roughness to the designed patterns on a EUV mask and to measure the response and sensitivity of CD-SEM and of the other techniques to these different pattern roughness levels once printed on wafers. This paper presents the roughness measurement results obtained with various metrology technologies including CD-SEM, OCD, S-TEM and XCD on EUV Lithography patterned wafers both postlithography and post-etch. The benefits of recently developed metrology enhancements are demonstrated as well; automated TEM allows to generate accurate and rather precise reference roughness data, Machine Learning enables OCD based roughness metrology with good correlation to CD-SEM and STEM, and the improved sensitivity of EUV and X-ray scattering systems allows to extract roughness information that does correlate to CD-SEM.

With the advent of high brightness sources and fast detectors, there is a possibility for combining fast X-ray acquisition with high-speed data treatment to reach the timescale for an effective in-line characterization method. We will highlight two recent developments using Small Angle X-ray Scattering on nanoscale etched patterns: the first is the inclusion of a CD-SAXS tool, allowing the data treatment and simulations to reconstruct the form-factor, inside the Xi-cam framework; the second is the development of a high performance Grazing Incidence approach to reconstruct the shape of line profile. This study also shows the comparison between the line profiles reconstructed from both techniques as well as the profile extracted from cross-section SEM.

Hybrid and data feed forward methodologies are well established for advanced optical process control solutions in highvolume semiconductor manufacturing. Appropriate information from previous measurements, transferred into advanced optical model(s) at following step(s), provides enhanced accuracy and exactness of the measured topographic (thicknesses, critical dimensions, etc.) and material parameters. In some cases, hybrid or feed-forward data are missed or invalid for dies or for a whole wafer. We focus on approaches of virtual metrology to re-create hybrid or feed-forward data inputs in high-volume manufacturing. We discuss missing data inputs reconstruction which is based on various interpolation and extrapolation schemes and uses information about wafer’s process history. Moreover, we demonstrate data reconstruction approach based on machine learning techniques utilizing optical model and measured spectra. And finally, we investigate metrics that allow one to assess error margin of virtual data input.

Data storage capacity of hard drive disks (HDD) has been increased over time. Partly this has been achieved by shrinking the dimensions of magnetic writing device also called the “main Pole”, a key magnetic flux emanating component in the slider that hovers over the magnetic media disk writing bits in nanoscale magnetic domains along the circular tracks. Even though the writer pole device is a single isolated device, its 3D shape and material composition are quite complex and critical dimensions are sub-50 nm. The reliability and accuracy of writing data in bits of magnetic nano-domains depends on the precise control of the pole shape and dimensions. Its fabrication requires over thousand process steps with many of them being various types of metrology steps. Final shape or back-end shape of the pole is influenced by various process steps and related information is captured by the subsequent metrology. Overlay, optical (thin film thickness using ellipsometry, topography using white light interferometry), CD-SEM, CD-AFM and inline FIB cross sections based metrology is commonly used. All this metrology data during fabrication process is called wafer metrology data. The data about the shape of the pole after device fabrication (lapping) is called back-end data and is obtained by cross section using FIB and SEM. Few device chips are sent ahead to determine the lapping parameters which takes time. This paper is about predicting the back-end shape parameters namely, pole height (PH), pole width (PW), and pole angle (PA), based on wafer data so that the backend metrology process requiring send-ahead can be optimized or even eliminated. Predictive models using machine learning and analytics techniques (neural networks, multivariate regression, and principal components analysis) have been studied and results will be presented and discussed in this paper. In this metrology centric data science study various steps have been pursued from the beginning to retrieve, integrate, transform, model, visualize data and understand the outcomes. Wafer data corresponding to more than seventy different parameters was used in this study. It is not possible to have all metrology data for each device as some techniques are destructive, imputation technique based on nearest neighbour data points is used. Model was trained and validated on a set of data and tested on an independent new data. Based on testing on independent data, study concludes that it is possible to train the model on data from few wafers for technology in production and predict the back-end pole shape parameters with acceptable accuracy for upcoming wafers. This could be very useful in reducing cycle time by minimizing the need for send ahead wafer components and optimizing the tuning of lapping process. Correlation of predicted (Y-axis) and measured (X-axis) values of PW parameters for four wafers is plotted in figure 1 at device level, flash field or exposure field level, and wafer level. The correlation between predicted and measured PW is reasonable for making use of the predictive model at the flash field level and wafer level to optimize the need for send ahead and determine the lapping parameters at back-end process.

In contrast to semiconductor manufacturing where features are mostly lines or contact holes, the disk drive reader has a complex, nonlinear 3D geometry. Metrology of such geometries is challenging; especially with regard to repeatability of measurements. New methods were needed to keep up with production requirements for metrology regarding uncertainty of critical dimensions (CD). We report a new method developed for CD metrology of the disk drive writer pole. The method demonstrated improved uncertainties compared to the regularly used CD-SEM algorithms and also has capability for side wall angle (SWA) metrology for process control. The method utilizes multiple steps: a) extract contours from SEM images, b) identify exact locations on a curvilinear feature where CD should be measured, and c) provide CD measurements at these locations. SEM images from a variety of production wafers were used for evaluation of the developed method. Multiple series of SEM images were processed using a software utilizing advanced algorithms without using regular brightness threshold CD-SEM methodologies. It was found that CD repeatability was improved by a factor of three compared to the results of the regular threshold based CD-SEM method. TEM imaging is used to measure side wall angle; it takes a lot of efforts for sample preparation and the feedback is slow. If extraction of SWA is possible from top down SEM images it would provide instant feedback to manufacturing and reduce cost. Monte Carlo simulations were used to understand the sensitivity of SWA to the trench CD and depth. Height of features was measured using AFM. A method to extract SWA from top down images was developed. Numerous SEM images were processed; results were compared to experiment and analyzed. It was shown that the 3-sigma repeatability of SWA measurement was 0.15 degree. It was also found that the left and the right SWA were different on multiple wafers, the results were very consistent from one image series to another one, at the same time the SWA difference between the left and right walls was considerably larger than the uncertainty of SWA measurement.

The interpretation of scanning electron microscopy (SEM) images of the latest semiconductor devices is not intuitive and requires comparison with computed images based on theoretical modeling and simulations. For quantitative image prediction and geometrical reconstruction of the specimen structure, the accuracy of the physical model is essential. In this paper, we review the current models of electron-solid interaction and discuss their accuracy. We perform the comparison of the simulated results with our experiments of SEM overlay of under-layer, grain imaging of copper interconnect, and hole bottom visualization by angular selective detectors, and show that our model well reproduces the experimental results. Remaining issues for quantitative simulation are also discussed, including the accuracy of the charge dynamics, treatment of beam skirt, and explosive increase in computing time.

Charging of insulators is a complex phenomenon to simulate since the accuracy of the simulations is very sensitive to the interaction of electrons with matter and electric fields. In this study, we report model improvements for a previously developed Monte-Carlo simulator to more accurately simulate samples that charge. The improvements include both modelling of low energy electron scattering and charging of insulators. The new first-principle scattering models provide a more realistic charge distribution cloud in the material, and a better match between non-charging simulations and experimental results. Improvements on charging models mainly focus on redistribution of the charge carriers in the material with an induced conductivity (EBIC) and a breakdown model, leading to a smoother distribution of the charges. Combined with a more accurate tracing of low energy electrons in the electric field, we managed to reproduce the dynamically changing charging contrast due to an induced positive surface potential.

Metrology plays an important role in edge placement error (EPE) budgeting. Control for multi-patterning applications as new critical distances needs to be measured (edge to edge) and requirements become tighter and tighter in terms of accuracy and precision. In this paper we focus on imec iN7 BEOL platform and particularly on M2 patterning scheme using SAQP + block EUV for a 7.5 track logic design. Being able to characterize block to SAQP edge misplacement is important in a budgeting exercise (1) but is also extremely difficult due to challenging edge detection with CD-SEM (similar materials, thin layers, short distances, 3D features). In this study we develop an advanced solution to measure block to SAQP placement, we characterize it in terms of sensitivity, precision and accuracy through the comparison to reference metrology. In a second phase, the methodology is applied to budget local effects and the results are compared to the characterization of the SAQP and block independently.

The influence of e-beam aperture angle on CD-SEM measurements for a high aspect ratio (HAR) structure was investigated. The Monte-Carlo simulator JMONSEL was used to evaluate the measurement sensitivity to the variation in the bottom CD. The aperture angle of the primary electron greatly influences the measurement accuracy of the bottom CD in the HAR structure. Then, we utilized a technique for energy-angular selective detection to the Monte-Carlo simulation results and found that the measurement sensitivity for the large aperture angle was improved. In addition, the experimental results were qualitatively consistent with the results of the Monte-Carlo simulation. These results indicate that the detection is effective for the bottom CD measurement of a HAR structure.

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the “more than Moore” path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or “virtual overlay” could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after litho control loop typically involves high frequency sampling: every lot or nearly every lot. An after etch overlay metrology step is often included, at a lower sampling frequency, in order to characterize and compensate for bias. The after etch metrology step often involves CD-SEM metrology, in this case in-cell and ondevice. This work explores an alternative approach using spectroscopic ellipsometry (SE) metrology and a machine learning analysis technique. Advanced 1x nm DRAM wafers were prepared, including both nominal (POR) wafers with mean overlay offsets, as well as DOE wafers with intentional across wafer overlay modulation. After litho metrology was measured using optical imaging metrology, as well as after etch metrology using both SE and CD-SEM for comparison. We investigate 2 types of machine learning techniques with SE data: model-less and model-based, showing excellent performance for after etch in-cell on-device overlay metrology.

Numerical simulation of overlay metrology targets has become a de-facto standard in advanced technology nodes. While appropriate simulation software is widely available in the industry alongside with metrics that allow selection of the best performing targets, the model validation tools are less developed. We present an approach of numerical model validation based on the comparison between target simulation results and on-product overlay measurements. A “simulation-tomeasurement” software is used in this work to compare the performance metrics and accuracy flags of scatterometrybased overlay targets designed using KLA-Tencor AcuRate™ simulator for the critical layers of 12nm FD-SOI FEOL stack and 22nm FD-SOI BEOL stack. We demonstrate how simulation-to-measurement matching enabled us to verify the model, identify discrepancies between the model and the product stack and build an improved model that correctly describes the target. The refined target stack was used for image-based overlay target simulations that allowed us to obtain better performing optical overlay targets as well.

Success of diffraction-based overlay (DBO) technique^1,4,5 in the industry is not just for its good precision and low toolinduced shift, but also for the measurement accuracy² and robustness that DBO can provide. Significant efforts are put in to capitalize on the potential that DBO has to address measurement accuracy and robustness. Introduction of many measurement wavelength choices (continuous wavelength) in DBO is one of the key new capabilities in this area. Along with the continuous choice of wavelengths, the algorithms (fueled by swing-curve physics) on how to use these wavelengths are of high importance for a robust recipe setup that can avoid the impact from process stack variations (symmetric as well as asymmetric). All these are discussed. Moreover, another aspect of boosting measurement accuracy and robustness is discussed that deploys the capability to combine overlay measurement data from multiple wavelength measurements. The goal is to provide a method to make overlay measurements immune from process stack variations and also to report health KPIs for every measurement. By combining measurements from multiple wavelengths, a final overlay measurement is generated. The results show a significant benefit in accuracy and robustness against process stack variation. These results are supported by both measurement data as well as simulation from many product stacks.

Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.

In next generation Logic devices, overlay control requirements shrink to sub 2.5nm level on-product overlay. Historically on-product overlay has been defined by the overlay capability of after-develop in-scribe targets. However, due to design and dimension, the after development metrology targets are not completely representative for the final overlay of the device. In addition, they are confined to the scribe-lane area, which limits the sampling possibilities. To address these two issues, metrology on structures matching the device structure and which can be sampled with high density across the device is required. Conventional after-etch CDSEM techniques on logic devices present difficulties in discerning the layers of interest, potential destructive charging effects and finally, they are limited by the long measurement times[1] [2] [3] . All together, limit the sampling densities and making CDSEM less attractive for control applications. Optical metrology can overcome most of these limitations. Such measurement, however, does require repetitive structures. This requirement is not fulfilled by logic devices, as the features vary in pitch and CD over the exposure field. The solution is to use small targets, with a maximum pad size of 5x5um² , which can easily be placed in the logic cell area. These targets share the process and architecture of the device features of interest, but with a modified design that replicates as close as possible the device layout, allowing for in-device metrology for both CD and Overlay. This solution enables measuring closer to the actual product feature location and, not being limited to scribe-lanes, it opens the possibility of higher-density sampling schemes across the field. In summary, these targets become the facilitator of in-device metrology (IDM), that is, enabling the measurements both in-device Overlay and the CD parameters of interest and can deliver accurate, high-throughput, dense and after-etch measurements for Logic. Overlay improvements derived from a high-densely sampled Overlay map measured with 5x5 um² In Device Metrology (IDM) targets were investigated on a customer Logic application. In this work we present both the main design aspects of the 5x5 um² IDM targets, as well as the results on the improved Overlay performance.

In semiconductor industry, fast and effective measurement of pattern variation has been key challenge for assuring massproduct quality. Pattern measurement techniques such as conventional CD-SEMs or Optical CDs have been extensively used, but these techniques are increasingly limited in terms of measurement throughput and time spent in modeling. In this paper we propose time effective pattern monitoring method through the direct spectrum-based approach. In this technique, a wavelength band sensitive to a specific pattern change is selected from spectroscopic ellipsometry signal scattered by pattern to be measured, and the amplitude and phase variation in the wavelength band are analyzed as a measurement index of the pattern change. This pattern change measurement technique is applied to several process steps and verified its applicability. Due to its fast and simple analysis, the methods can be adapted to the massive process variation monitoring maximizing measurement throughput.

Power spectral density (PSD) analysis is playing more and more a critical role in the understanding of line-edge roughness (LER) and linewidth roughness (LWR) in a variety of applications across the industry. It is an essential step to get an unbiased LWR estimate, as well as an extremely useful tool for process and material characterization. However, PSD estimate can be affected by both random to systematic artifacts caused by image acquisition and measurement settings, which could irremediably alter its information content. In this paper, we report on the impact of various setting parameters (smoothing image processing filters, pixel size, and SEM noise levels) on the PSD estimate. We discuss also the use of PSD analysis tool in a variety of cases. Looking beyond the basic roughness estimate, we use PSD and autocorrelation analysis to characterize resist blur[1], as well as low and high frequency roughness contents and we apply this technique to guide the EUV material stack selection. Our results clearly indicate that, if properly used, PSD methodology is a very sensitive tool to investigate material and process variations

In this paper, we discuss the metrology methods and error budget that describe the edge placement error (EPE). EPE quantifies the pattern fidelity of a device structure made in a multi-patterning scheme. Here the pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. EPE is computed by combining optical and ebeam metrology data. We show that high NA optical scatterometer can be used to densely measure in device CD and overlay errors. Large field e-beam system enables massive CD metrology which is used to characterize the local CD error. Local CD distribution needs to be characterized beyond 6 sigma, and requires high throughput e-beam system. We present in this paper the first images of a multi-beam e-beam inspection system. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As a use case, we evaluated a 5-nm logic patterning process based on Self-Aligned-QuadruplePatterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography.

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a ‘fingerprint’, on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel ‘computational process control strategy’ which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Immersion lithography is being extended beyond the 10-nm node and the lithography performance requirement needs to be tightened further to ensure good yield. Amongst others, good on-product focus control with accurate and dense metrology measurements is essential to enable this. In this paper, we will present new solutions that enable onproduct focus monitoring and control (mean and uniformity) suitable for high volume manufacturing environment. We will introduce the concept of pure focus and its role in focus control through the imaging optimizer scanner correction interface. The results will show that the focus uniformity can be improved by up to 25%.

Computational metrology has been proposed as the way forward to resolve the need for increased metrology density, resulting from extending correction capabilities, without adding actual metrology budget. By exploiting TWINSCAN based metrology information, dense overlay fingerprints for every wafer can be computed. This extended metrology dataset enables new use cases, such as monitoring and control based on fingerprints for every wafer of the lot. This paper gives a detailed description, discusses the accuracy of the fingerprints computed, and will show results obtained in a DRAM HVM manufacturing environment. Also an outlook for improvements and extensions will be shared.

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing “measuring what matters” and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.

A machine-learning model is presented that effectively partitions historical process data into outlier and inlier subpopulations. This is necessary in order to avoid using outlier data to build a model for detecting process instability. Exact control limits are given without recourse to approximations and the error characteristics of the control model are derived. A worked example for contamination control is presented along with the machine learning algorithm used and all the programming statements needed for implementation.

Overlay errors between two layers can be caused by non-lithography processes. While these errors can be compensated by the run-to-run system, such process and tool signatures are not always stable. In order to monitor the impact of non-lithography context on overlay at regular intervals, a systematic approach is needed. Using various machine learning techniques, significant context parameters that relate to deviating overlay signatures are automatically identified. Once the most influential context parameters are found, a run-to-run simulation is performed to see how much improvement can be obtained. The resulting analysis shows good potential for reducing the influence of hidden context parameters on overlay performance. Non-lithographic contexts are significant contributors, and their automatic detection and classification will enable the overlay roadmap, given the corresponding control capabilities.

Mask registration data are presented, which demonstrate local errors that can be correlated to writing swathes of state-of-the-art e-beam writers and multi-pass strategies. A unique measurement methodology, Local Registration Metrology, allows for dense sampling of reticle dies to characterize the local e-beam registration error and enables e-beam corrections via feed forward.

Recently, a novel method for the calculation of unbiased Line Edge Roughness based on Power Spectral Density analysis has been proposed. In this paper first an alternative method is discussed and investigated, utilizing the Height-Height Correlation Function (HHCF) of edges. The HHCF-based method enables the unbiased determination of the whole triplet of LER parameters including besides rms the correlation length and roughness exponent. The key of both methods is the sensitivity of PSD and HHCF on noise at high frequencies and short distance respectively. Secondly, we elaborate a testbed of synthesized SEM images with controlled LER and noise to justify the effectiveness of the proposed unbiased methods. Our main objective is to find out the boundaries of the method in respect to noise levels and roughness characteristics, for which the method remains reliable, i.e the maximum amount of noise allowed, for which the output results cope with the controllable known inputs. At the same time, we will also set the extremes of roughness parameters for which the methods hold their accuracy.

General approaches to realize higher sensitivity in optical inspection system are using shorter wavelength including UV and higher NA for objective lens. Extreme performances of imaging and illumination systems in a situation of wellmatched to each other are inevitable for the further effort on an effective optical detection of fine defects in patterned wafer. This study focused on the dark-field illumination method in near-field condition with simple modification of far-field imaging and illumination system which is designed by anamorphic optics and the potential of it is derived from experimental methods.

Recently the aspect ratio of capacitor and via hole of memory semiconductor device has been dramatically increasing in order to store more information in a limited area. A small amount of remained residues after etch process on the bottom of the high aspect ratio structure can make a critical failure in device operation. Back-scattered electrons (BSE) are mainly used for inspecting the defect located at the bottom of the high aspect ratio structure or analyzing the overlay of the multi-layer structure because these electrons have a high linearity with the direction of emission and a high kinetic energy above 50eV. However, there is a limitation on that it cannot detect ultra-thin residue material having a thickness of several nanometers because the surface sensitivity is extremely low. We studied the characteristics of BSE spectra using Monte Carlo simulations for several cases which the high aspect ratio structures have extreme microscopic residues. Based on the assumption that most of the electrons emitted without energy loss are localized on the surface, we selected the detection energy window which has a range of 20eV below the maximum energy of the BSE. This window section is named as the high-energy BSE region. As a result of comparing the detection sensitivity of the conventional and the high-energy BSE detection mode, we found that the detection sensitivity for the residuals which have 2nm thickness is improved by more than 10 times in the high-energy BSE mode. This BSE technology is a new inspection method that can greatly be improved the inspection sensitivity for the ultra-thin residual material presented in the high aspect ratio structure, and its application will be expanded.

Accurate EPE (edge placement error) characterization is important for the process control of high-volume manufacturing at N5 BEOL and beyond. In a CD-SEM metrology, the accurate edge-to-edge measurements among multiple layers and/or SEM-Contour extraction are required for the accurate EPE characterization. One of the technical challenges in CD-SEM metrology is to control charging effects caused by EB-irradiation during SEM image acquisition. In this paper, the effects of new charge control methods (Special Scan and Faster Scan), which are implemented in the latest Hitachi CD-SEM (CG6300), were examined with EUV resist hole-patterns. It was confirmed that Special Scan showed a profound effect on the suppression of the charge-induced errors. We also demonstrated the effects of the Special Scan for CD measurements and Contour Extraction for the EPE characterization of block on SAQP (SAQP lines + EUV block) pattern at imec iN7platform. Consequently, Special Scan is expected to be the solution for the accurate EPE measurements by CD-SEM.

Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and known to increase with the introduction of EUV lithography. However, despite recommendations from ITRS, NIST, and SEMI standards, the industry has not agreed upon a methodology to quantify these properties. Thus, differing methodologies applied to the same image often result in different roughness measurements and conclusions. To standardize LWR and LER measurements, Fractilia has developed an unbiased measurement that uses a raw unfiltered line scan to subtract out image noise and distortions. By using Fractilia’s inverse linescan model (FILM) to guide development, we will highlight the key influences of roughness metrology on plasma-based resist smoothing processes. Test wafers were deposited to represent a 5 nm node EUV logic stack. The patterning stack consists of a core Si target layer with spin-on carbon (SOC) as the hardmask and spin-on glass (SOG) as the cap. Next, these wafers were exposed through an ASML NXE 3350B EUV scanner with an advanced chemically amplified resist (CAR). Afterwards, these wafers were etched through a variety of plasma-based resist smoothing techniques using a Lam Kiyo conductor etch system. Dense line and space patterns on the etched samples were imaged through advanced Hitachi CDSEMs and the LER and LWR were measured through both Fractilia and an industry standard roughness measurement software. By employing Fractilia to guide plasma-based etch development, we demonstrate that Fractilia produces accurate roughness measurements on resist in contrast to an industry standard measurement software. These results highlight the importance of subtracting out SEM image noise to obtain quicker developmental cycle times and lower target layer roughness.

We present an experimental study of pattern variability and defectivity, based on a large data set with more than 112 million SEM measurements from an HMI high-throughput e-beam tool. The test case is a 10nm node SRAM via array patterned with a DUV immersion LELE process, where we see a variation in mean size and litho sensitivities between different unique via patterns that leads to a seemingly qualitative differences in defectivity. The large available data volume enables further analysis to reliably distinguish global and local CDU variations, including a breakdown into local systematics and stochastics. A closer inspection of the tail end of the distributions and estimation of defect probabilities concludes that there is a common defect mechanism and defect threshold despite the observed differences of specific pattern characteristics. We expect that the analysis methodology can be applied for defect probability modeling as well as general process qualification in the future.

For EUV lithography features we want to decrease the dose and/or energy of CD-SEM’s probe beam because LER decreases with severe resist-material’s shrink. Under such conditions, however, measured LER increases from true LER, due to LER bias that is fake LER caused by random noise in SEM image. A gap error occurs between the right and the left LERs. In this work we propose new procedures to obtain true LER by excluding the LER bias from the measured LER. To verify it we propose a LER’s reference-metrology using TEM.

With the increase of litho-etch steps the industry requires metrology to deliver solutions to improve throughput of overlay measurements without impacting accuracy. ASML’s YieldStar 350E is capable of utilizing targets, which can measure the overlay of multiple layers simultaneously. For the work discussed in this paper, an evaluation is performed on Logic product wafers using both single-layer and multi-layer (MLT) quad type targets (able to capture up to four litho-etch steps). Different target types were compared in terms of Move-and-Acquire (MA) time, residual and matching to SEM. Using the MLT targets, an MA time improvement of 56% was demonstrated on the singlelayer. The maximum delta between the overlay residual among the YieldStar targets after applying an high order model was shown to be 0.05 nm. In comparison to after-etch overlay, the correlation of the MLT target was determined with an R² >; 0.95 using a set-get wafer with induced 10 nm overlay range. On a normal production wafer, the correlation was R² > 0.67, which is high on a wafer without induced overlay. The comparison of modeling parameters between SEM and MLT targets shows a good match (< 0.16nm) as well.

In the discussion of edge placement error (EPE), we proposed interactive pattern fidelity error (IPFE) as an indicator to judge pass/fail of integrated patterns. IPFE consists of lower and upper layer EPEs (CD and center of gravity: COG) and overlay, which is decided from the combination of each maximum variation. We succeeded in obtaining the IPFE density function by Monte Carlo simulation. In the results, we also found that the standard deviation (σ) of each indicator should be controlled by 4.0σ, at the semiconductor grade, such as 100 billion patterns per die. Moreover, CD, COG and overlay were analyzed by analysis of variance (ANOVA); we can discuss all variations from wafer to wafer (WTW), pattern to pattern (PTP), line edge roughness (LWR) and stochastic pattern noise (SPN) on an equal footing. From the analysis results, we can determine that these variations belong to which process and tools. Furthermore, measurement length of LWR is also discussed in ANOVA. We propose that the measurement length for IPFE analysis should not be decided to the micro meter order, such as >2 μm length, but for which device is actually desired.

Lithography process control solutions require more exacting capabilities as the semiconductor industry goes forward to the 1x nm node DRAM device manufacturing. In order to continue scaling down the device feature sizes, critical dimension (CD) uniformity requires continuous improvement to meet the required CD error budget. In this study we investigate using optical measurement technology to improve over CD-SEM methods in focus, dose, and CD. One of the key challenges is measuring scanner focus of device patterns. There are focus measurement methods based on specially designed marks on scribe-line, however, one issue of this approach is that it will report focus of scribe line which is potentially different from that of the real device pattern. In addition, scribe-line marks require additional design and troubleshooting steps that add complexity. In this study, we investigated focus measurement directly on the device pattern. Dose control is typically based on using the linear correlation behavior between dose and CD. The noise of CD measurement, based on CD-SEM for example, will not only impact the accuracy, but also will make it difficult to monitor dose signature on product wafers. In this study we will report the direct dose metrology result using an optical metrology system which especially enhances the DUV spectral coverage to improve the signal to noise ratio. CD-SEM is often used to measure CD after the lithography step. This measurement approach has the advantage of easy recipe setup as well as the flexibility to measure critical feature dimensions, however, we observe that CD-SEM metrology has limitations. In this study, we demonstrate within-field CD uniformity improvement through the extraction of clean scanner slit and scan CD behavior by using optical metrology.

To reduce charging and shrinkage, CD-SEMs utilize low electron energies and multiframe imaging. This results in every next frame being altered due to stage and beam instability, as well as due to charging. Regular averaging of the frames blurs the edges; this directly effects the extracted values of critical dimensions. A technique was developed to overlay multiframe images without the loss of quality. This method takes into account drift, rotation, and magnification corrections, as well as nonlinear distortions due to wafer charging. A significant improvement in the signal to noise ratio and overall image quality without degradation of the feature’s edge quality was achieved. The developed software is capable of working with regular and large size images up to 32K pixels in each direction.

Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.

We report on advanced defect classification using TNO’s RapidNano particle scanner. RapidNano was originally designed for defect detection on blank substrates. In detection-mode, the RapidNano signal from nine azimuth angles is added for sensitivity. In review-mode signals from individual angles are analyzed to derive additional defect properties. We define the Fourier coefficient parameter space that is useful to study the statistical variation in defect types on a sample. By selecting defects from each defect type for further review by SEM, information on all defects can be obtained efficiently.

We have been developing a charging simulator “CHARMs”, which is based on 3D finite element method, to predict the characteristics of signal from charged pattern on surface of semi-conductor during the SEM observation. We have constructed a new flexible model to simulate the in-solid electron scattering by the Langevin equation for “CHARMs”. Our new model can manipulate the size of the diffusion cloud of scattering electron by the parameters of it and calculate ten times faster than the conventional Monte Carlo (MC) method. In addition to that, the model has the possibility to accurately describe the scattering of low energy electron. We also confirmed that the same results of the conventional MC method can be obtained from the simulation model of metal pattern buried in the sample.

As design pitch shrinks to the resolution limit of up-to-date optical lithography technology, the Critical Dimension (CD) variation tolerance has been dramatically decreased for ensuring the functionality of device. One of critical challenges associates with the narrower CD tolerance for whole chip area is the proximity effect control on asymmetrical layout environments. To fulfill the tight CD control of complex features, the Critical Dimension Scanning Electron Microscope (CD-SEM) based measurement results for qualifying process window and establishing the Optical Proximity Correction (OPC) model become insufficient, thus 2D contour extraction technique [1-5] has been an increasingly important approach for complementing the insufficiencies of traditional CD measurement algorithm. To alleviate the long cycle time and high cost penalties for product verification, manufacturing requirements are better to be well handled at design stage to improve the quality and yield of ICs. In this work, in-house 2D contour extraction platform was established for layout design optimization of 39nm half-pitch Self-Aligned Double Patterning (SADP) process layer. Combining with the adoption of Process Variation Band Index (PVBI), the contour extraction platform enables layout optimization speedup as comparing to traditional methods. The capabilities of identifying and handling lithography hotspots in complex layout environments of 2D contour extraction platform allow process window aware layout optimization to meet the manufacturing requirements.

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP’s standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

In fabrication, overlay measurements of semiconductor device patterns have conventionally been performed using optical methods. Beginning with image-based techniques using box-in-box to the more recent diffraction-based overlay (DBO). Alternatively, use of SEM overlay is under consideration for in-device overlay. Two main application spaces are measurement features from multiple mask levels on the same surface and buried features. Modern CD-SEMs are adept at measuring overlay for cases where all features are on the surface. In order to measure overlay of buried features, HV-SEM is needed. Gate-to-fin and BEOL overlay are important use cases for this technique. A JMONSEL simulation exercise was performed for these two cases using 10 nm line/space gratings of graduated increase in depth of burial. Backscattered energy loss results of these simulations were used to calculate the sensitivity measurements of buried features versus electron dosage for an array of electron beam voltages.

We present preliminary through-pellicle imaging using a 30nm tabletop extreme ultraviolet (EUV) coherent diffractive imaging microscope. We show that even in a non-optimized setup, this technique enables through-pellicle imaging of a sample with no detectable impact on image fidelity or resolution.

Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is >100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.

Cutting edge innovation requires accurate and fast process-control to obtain fast learning rate and industry adoption. Current tools available for such task are mainly manual and user dependent. We present in this paper cognitive learning, which is a new machine learning based technique to facilitate and to speed up complex characterization by using the design as input, providing fast training and detection time. We will focus on the machine learning framework that allows object detection, defect traceability and automatic measurement tools.

A new metrology method of quantitatively measuring wiggling patterns in a Self-Aligned Double Patterning (SADP) process for 2D NAND technology has been developed with a CD-SEM metrology program on images from a Review-SEM system. The metrology program provided accurate modeling of various wiggling patterns. The Review-SEM system provided a-few-micrometer-wide Field of View (FOV), which exceeds precision-guaranteed FOV of a conventional CD-SEM. The result has been effectively verified by visual inspection on vertically compressed images compared with Wiggling Index from this new method. A best-known method (BKM) system has been developed with connected HW and SW to automatically measure wiggling patterns.

In a 200 mm high volume environment, we studied data from a dual damascene process. Dual damascene is a combination of lithography, etch and CMP that is used to create copper lines and contacts in one single step. During these process steps, different metal CD are measured by different measurement methods. In this study, we analyze the key numbers of the different measurements after different process steps and develop simple models to predict the electrical behavior* . In addition, radial profiles have been analyzed of both inline measurement parameters and electrical parameters. A matching method was developed based on inline and electrical data. Finally, correlation analysis for radial signatures is presented that can be used to predict excursions in electrical signatures.

As the feature size is shrinking in the foundries, the need for inline high resolution surface profiling with versatile capabilities is increasing. One of the important areas of this need is chemical mechanical planarization (CMP) process. We introduce a new generation of atomic force profiler (AFP) using decoupled scanners design. The system is capable of providing small-scale profiling using XY scanner and large-scale profiling using sliding stage. Decoupled scanners design enables enhanced vision which helps minimizing the positioning error for locations of interest in case of highly polished dies. Non-Contact mode imaging is another feature of interest in this system which is used for surface roughness measurement, automatic defect review, and deep trench measurement. Examples of the measurements performed using the atomic force profiler are demonstrated.

Severe process margin in advanced technology node of semiconductor device is controlled by e-beam metrology system and e-beam inspection system with scanning electron microscopy (SEM) image. By using SEM, larger area image with higher image quality is required to collect massive amount of data for metrology and to detect defect in a large area for inspection. Although photoresist is the one of the critical process in semiconductor device manufacturing, observing photoresist pattern by SEM image is crucial and troublesome especially in the case of large image. The charging effect by e-beam irradiation on photoresist pattern causes deterioration of image quality, and it affect CD variation on metrology system and causes difficulties to continue defect inspection in a long time for a large area. In this study, we established a quantitative approach for optimizing e-beam condition with “Die to Database” algorithm of NGR3500 on photoresist pattern to minimize charging effect. And we enhanced the performance of measurement and inspection on photoresist pattern by using optimized e-beam condition. NGR3500 is the geometry verification system based on “Die to Database” algorithm which compares SEM image with design data [1]. By comparing SEM image and design data, key performance indicator (KPI) of SEM image such as "Sharpness", "S/N", "Gray level variation in FOV", "Image shift" can be retrieved. These KPIs were analyzed with different e-beam conditions which consist of “Landing Energy”, “Probe Current”, “Scanning Speed” and “Scanning Method”, and the best e-beam condition could be achieved with maximum image quality, maximum scanning speed and minimum image shift. On this quantitative approach of optimizing e-beam condition, we could observe dependency of SEM condition on photoresist charging. By using optimized e-beam condition, measurement could be continued on photoresist pattern over 24 hours stably. KPIs of SEM image proved image quality during measurement and inspection was stabled enough.

New materials and designs in complex 3D architectures in logic and memory devices have raised complexity in S/TEM metrology. In this paper, we report about a newly developed, automated, scanning transmission electron microscopy (STEM) based, energy dispersive X-ray spectroscopy (STEM-EDS) metrology method that addresses these challenges. Different methodologies toward repeatable and efficient, automated STEM-EDS metrology with high throughput are presented: we introduce the best known auto-EDS acquisition and quantification methods for robust and reliable metrology and present how electron exposure dose impacts the EDS metrology reproducibility, either due to poor signalto-noise ratio (SNR) at low dose or due to sample modifications at high dose conditions. Finally, we discuss the limitations of the STEM-EDS metrology technique and propose strategies to optimize the process both in terms of throughput and metrology reliability.

Defects in ultra-thin films appear as small perturbations in the measured optical dispersion using spectroscopic ellipsometry (SE). A common approach for quantifying these defects is to fit each pixel in the dispersion to an index of refraction and extinction coefficient for a known material thickness (point-by-point method). However, this point-bypoint method is not physical because it produces dispersions that are not Kramers-Kronig consistent and it is also subject to overfitting. In this work, we demonstrate that the Kramers-Kronig consistent Cody Lorentz Multiple-Oscillator model (CLM) can precisely quantify defects in HfO₂ using the Lorentz peak amplitude dispersion parameter as one of the fitting parameters. Using a KLA-Tencor spectroscopic ellipsometer, we collected optical dispersions of ultra-thin HfO₂ grown on SiO₂ for a variety of growth parameters including HfO₂ thickness, SiO₂ thickness, and anneal time, and then have used CLM to quantify the defects. The HfO₂ defect value was found to successfully track the different growth conditions, which is consistent with literature, and the defect values have little within-wafer variance. Quantifying defects in a material sub-bandgap successfully will provide information about leakage currents and device performance for gated semiconductor devices.

One of the main components of an On-Product Overlay (OPO) error budget is the process induced wafer error. This necessitates wafer-to-wafer correction in order to optimize overlay accuracy. This paper introduces the Litho Booster (LB), standalone alignment station as a solution to improving OPO. LB can execute high speed alignment measurements without throughput (THP) loss. LB can be installed in any lithography process control loop as a metrology tool, and is then able to provide feed-forward (FF) corrections to the scanners. In this paper, the detailed LB design is described and basic LB performance and OPO improvement is demonstrated. Litho Booster’s extendibility and applicability as a solution for next generation manufacturing accuracy and productivity challenges are also outlined

Over the years, mask and wafers defects dispositioning has become an increasingly challenging and time consuming task. With design rules getting smaller, OPC getting complex and scanner illumination taking on free-form shapes - the probability of a user to perform accurate and repeatable classification of defects detected by mask inspection tools into pass/fail bins is reducing. The critical challenging of mask defect metrology for small nodes ( < 30 nm) was reviewed in [1]. While Critical Dimension (CD) variation measurement is still the method of choice for determining a mask defect future impact on wafer, the high complexity of OPCs combined with high variability in pattern shapes poses a challenge for any automated CD variation measurement method. In this study, a novel approach for measurement generalization is presented. CD variation assessment performance is evaluated on multiple different complex shape patterns, and is benchmarked against an existing qualified measurement methodology.

As semiconductor manufacturing technology progresses and the dimensions of integrated circuit elements shrink, overlay budget is accordingly being reduced. Overlay budget closely approaches the scale of measurement inaccuracies due to both optical imperfections of the measurement system and the interaction of light with geometrical asymmetries of the measured targets. Measurement inaccuracies can no longer be ignored due to their significant effect on the resulting device yield. In this paper we investigate a new approach for imaging based overlay (IBO) measurements by optimizing accuracy rather than contrast precision, including its effect over the total target performance, using wavelength tunable overlay imaging metrology. We present new accuracy metrics based on theoretical development and present their quality in identifying the measurement accuracy when compared to CD-SEM overlay measurements. The paper presents the theoretical considerations and simulation work, as well as measurement data, for which tunability combined with the new accuracy metrics is shown to improve accuracy performance.

Due to its potential for high resolution and three-dimensional imaging, soft x-ray ptychography has received interest for nanometrology applications. We have analyzed the measurement time per unit area when using soft x-ray ptychography for various nanometrology applications including mask inspection and wafer inspection, and are thus able to predict (order of magnitude) throughput figures. Here we show that for a typical measurement system, using a typical sampling strategy, and when aiming for 10-15 nm resolution, it is expected that a wafer-based topology (2.5D) measurement takes approximately 4 minutes per μm² , and a full three-dimensional measurement takes roughly 6 hours per μm² . Due to their much higher reflectivity EUV masks can be measured considerably faster; a measurement speed of 0.1 seconds per μm² is expected. However, such speeds do not allow for full wafer or mask inspection at industrially relevant throughput.

In this paper, we propose to rethink the issue of LER characterization on the basis of the fundamental concept of symmetries. In LER one can apply two kinds of symmetries: a) the translation symmetry characterized by periodicity and b) the scaling symmetry quantified by the fractal dimension. Up to now, a lot of work has been done on the first symmetry since the Power Spectral Density (PSD), which has been extensively studied recently, is a decomposition of LER signal into periodic edges and quantification of the ‘power’ of each periodicity at the real LER. The aim of this paper is to focus on the second symmetry of scaling invariance. Similarly to PSD, we introduce the multifractal approach in LER analysis which generalizes the scaling analysis of standard (mono)fractal theory and decomposes LER into fractal edges characterized by specific fractal dimensions. The main benefit of multifractal analysis is that it enables the characterization of the multi-scaling contributions of different mechanisms involved in LER formation. In the first part of our work, we present concisely the multifractal theory of line edges and utilize the Box Counting method for its implementation and the extraction of the multifractal spectrum. Special emphasis is given on the explanation of the physical meaning of the obtained multifractal spectrum whose asymmetry quantifies the degree of multifractality. In addition, we propose the distinction between peak-based and valley-based multifractality according to whether the asymmetry of the multifractal spectrum is coming from the sharp line material peaks to space regions or from the cavities of line materis (edge valleys). In the second part, we study systematically the evolution of LER multifractal spectrum during the first successive steps of a multiple (quadruple) patterning lithography technique and find an interesting transition from a peak-based multifractal behavior in the first litho resist LER to a valley-based multifractality caused mainly by the effects of etch pattern transfer steps.

In this paper, we focus on our most advanced multiple beam technology and next generation multiple beam inspector(MBI) development. We have successfully got 9 images on primary beam module, proving our design concept is correct. We also discussed related technologies, e.g. Computation and fast stage technology to further improve throughput and lower COO. At last MBI new applications are discussed.