Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm node. Critical comparison between conventional ArF lithography and PEL as to the via-chain yield for test element groups (TEGs) including approximately 2.9 million via chains was performed to demonstrate its production feasibility.
We report the first evaluation results for the printability and detectability of mask defects on a 1x stencil mask as used for proximity electron lithography (PEL). The defect printability has been defined for the patterns after the multi-step etching process through the tri-layer resist system inherently required for the use of low-energy electrons and the substrate. According to the three-dimensional lithography simulation, this definition is preferable to the conventional one based on the resist patterns prior to the etching process in the point that smoothing effects on defects are automatically taken into account. The critical size of printable defects as defined is 22 nm for 140 nm contact holes, while the stringent value of 16 nm is predicted in the conventional definition. Also, the detectability of the printable defects has been assessed by using the transmission electron-beam (EB) inspection tool. The assessment has been performed for both programmed defects and real defects occurred in contact-hole arrays. For the programmed defects, the perfect repeatability has been demonstrated for all the defects with printable sizes. In addition, real defects with the size of 15 nm have been successfully detected in the contact-hole arrays. Therefore, this study has demonstrated the manufacturability of PEL masks from the viewpoint of defect inspection.
The lithographic performance of the low-energy electron-beam proximity-projection lithography (LEEPL) tool is demonstrated in terms of printability and overlay accuracy to establish the feasibility of proximity electron lithography (PEL) for the 65-nm technology node. The CD uniformity of 5.8 nm is achieved for the 1× stencil mask, and the mask patterns are transferred onto chemically amplified resist layers, coupled with a conformal multilayer process with the mask-error enhancement factor of nearly unity. Meanwhile, the overlay accuracy of 27.8 nm is achieved in the context of mix and match with the ArF scanner, and it is also shown that real-time correction for chip magnification, enabled by the use of die-by-die alignment and electron beam, can further reduce the error down to 21.3 nm. On the basis of the printability of programmed defects, it is shown that the most critical challenge to be solved for the application to production is the quality assurance of masks such as defect inspection and repair.
Low-energy electron-beam proximity-projection lithography (LEEPL) is considered the best candidate for the next-generation lithography (NGL) tool because a production tool will be available for 65nm-node mass production. Resolution capability has already exceeded the 65nm-node requirement and possibly also the 45nm-node requirement. Although LEEPL requires a resist less than 100nm thick to obtain the resolution, our tri-layer resist process provides the critical-dimension (CD) uniformity and dry-etching resistance necessary for fabricating 90nm-node via holes. As regards an overlay, a LEEPL tool aligned to an under layer printed by an ArF scanner attained 21.3nm (three sigma) overlay error, which exceeds the requirement for the 65nm node. Another concern with LEEPL application is mask contamination growth during exposure, however the contamination growth rate is gradual that the CD shift due to the contamination is under control. We applied LEEPL to 90nm-node via hole fabrication to examine whether it provides a higher resolution than an ArF scanner. We determined that the electrical-resistance limit for LEEPL is approximately 100nm diameter for a via hole and the limit for an ArF scanner is approximately 125nm diameter. Even without process optimization, LEEPL showed its advantages for via-hole fabrication over an ArF scanner.
The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 mm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.
The critical-dimension (CD) performance and the printability of 1x stencil masks used for low-energy electron-beam proximity-projection lithography (LEEPL) have been studied by using the LEEPL β-tool. The CD uniformity and the line edge roughness on the mask are 6.0 nm and 3.5 nm in 3σ, respectively. It has been found that the fidelity of the etching process is so high that the optimization of the electron-beam writing process is critical to perforate high-quality patterns. The mask error enhancement factor evaluated over 80-100 nm lies is nearly unity, demonstrating the excellent fidelity of image transfer from the mask to a wafer. The critical defect sizes are 14.5 and 22.8 nm for the protrusions on the edges of 100-nm lines and the 150-nm contact holes respectively, implying that defect inspection is a challenge. The current achievements and the final targets in the 65-nm node are compared to assess the gap that must be bridged.
We propose the efficient on-site use of a 1x stencil mask for proximity electron lithography (PEL) for controlling image placement (IP) and critical dimension (CD). It has been demonstrated that the integrated approach to the IP-error correction on the mask-fabrication level using the data manipulation and the mask-exposure level using the deflection of an electron beam (EB) can meet the requirement for the overlay accuracy in the 65-nm technology node. Also, the time-dependent variation in mask CD due to EB-assisted contamination growth can be managed by using the combination of the dose control and the periodic dry cleaning of the mask.
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