Semiconductors have spurred the greatest period of technological advancement in human history, transforming every aspect of our lives. As a result, information and communication technologies (ICT) are seeing "super-exponential growth." But, starting in late 2020, SRC highlighted that the demands for ICT are encroaching on global energy production levels. Even with all of the improvements that 2D-scaling and Moore's law have afforded semiconductors, an insatiable global appetite for ICT is yielding energy consumption levels that are the new headwind for its continued advancement. We must invest in and deliver new paradigms at scale with a radically improved (106:1) energy efficiency. This unprecedented production also meets a time where global sustainability has never been more important. As an R&D community, we have an obligation to ensure that the growth in chip manufacturing and packaged chip volumes is as environmentally benign as possible and does not stress our already taxed planet. And, most importantly, our industry faces a workforce shortage where the next generation of innovators demands that their efforts positively contribute to a better future, for both society and the environment. In response to these critical factors, SRC, in partnership with NIST, worked with 298 individuals representing 112 industrial, academic, and government organizations to create and publish the Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap. It is a plan to revitalize the semiconductor industry for decades to meet the market, workforce, and sustainability needs of our collective future.

The worldwide demand for computing is undergoing a notable shift, driven by factors like AI/ML, the need for ubiquitous connectivity, and a focus on energy efficiency. In pursuit of the industry's commitment to continuous innovation at Moore’s Law cadence, a system technology co-optimization (STCO) approach has been embraced. Consequently, the distinctions between silicon technology and advanced packaging are blurring. This keynote delves into the evolution of advanced lithography and patterning in the STCO era of Moore’s Law, highlighting the ongoing progress in both silicon and advanced packaging. The importance of sharing ecosystem expertise and ideas across silicon and advanced packaging is underscored for reaping significant benefits. Additionally, with the industry aiming to surpass the $1 trillion revenue mark by the end of the decade, the imperative to innovate on the ongoing journey to environmentally sustainable technologies is emphasized.

High density memory device has become an inevitable demand of processing capabilities and storage in various applications. The high-density memory devices been mainly developed by lithography, the lateral-scaling technology. In 2010s, DUV multi-patterning technique was introduced as a main contributor of the lateral-scaling, which however recently comes at the cost due to expanding of quadruple patterning and reduction of process margin. As a result, EUV lithography has joined into dominant patterning options for maximizing patterning resolution and reducing cost. This paper presents our latest patterning solutions extending patterning limit beyond sub 10nm, and outlook of future technologies on memory device patterning such as EUV, High-NA, 3D structure, and bonding overlay.

This conference presentation was prepared for Optical and EUV Nanolithography XXXVII, 2024.

This conference presentation was prepared for Optical and EUV Nanolithography XXXVII, 2024.

This conference presentation was prepared for Optical and EUV Nanolithography XXXVII, 2024.

This conference presentation was prepared for Optical and EUV Nanolithography XXXVII, 2024.

This conference presentation was prepared for Optical and EUV Nanolithography XXXVII, 2024.

We are in a race to create Artificial Super Intelligence (ASI) that can exceed the capabilities of the human brain. This quest is the moonshot of next-generation engineers and scientists alike, and the path to this realization starts with semiconductor technology. Supported by advancements in semiconductor technology, we are making significant progress in the areas of Artificial Narrow Intelligence (ANI) and Artificial General Intelligence (AGI) and are now within grasp of Artificial Super Intelligence (ASI). As we watch this journey unfold in front of our eyes, memory is becoming central to our progress. This is substantiated by the fact that bit shipments have increased by 12X for DRAM, and 48X for NAND, just in the last decade! The progress we have driven to date is something we can all be proud of but is still not enough to answer bigger questions and resolve greater challenges that can only be addressed by enabling more advanced technology in our field. And as we enable more advanced technology, we must continue to ask ourselves a few key questions, to ensure we are growing these capabilities in a sustainable and ethical manner.

Accurate data for optical properties are essential for the design of new materials needed for EUV mask absorber layers, photoresists and pellicles. Fortunately, in the EUV we are able to use the independent atom approximation to estimate the index of refraction for complex materials from the atomic scattering factors. CXRO maintains a database of the atomic scattering factors. Improving the accuracy of this database relies on the accurate measurements of the elements. Measurements with improved accuracy over a broad range of wavelengths are being performed at synchrotron facilities around the world. Recent advances will be discussed.

Considering potential negative impacts on the scanner, such as the shortened life duration of scanner optical components due to increased pulse energy, from conventional scaling, not only the increase in Repetition Rate (RR) but also reduction of effects on optical components need to be addressed. Furthermore, for improvement in EPE, apart from high RR scaling and minimizing optical component impacts, reduction in Line Width Roughness (LWR) and Line Edge Roughness (LER) caused by speckle is also put into account.

Speckle can be reduced through increased laser bandwidth co-optimized with SMO-OPC. Figure 1 is a plot of calculated speckle contrast for the Cymer 860ix laser that is coupled with the ASML NXT 2000 scanner and the Cymer 960ix coupled with the ASML NXT 2050 scanner with the increased pulse duration (TIS is time integral squared) vs laser bandwidth. We focus on 300fm speckle contrast for the XLR 960ix (blue) and the XLR 860ix (red) at 640fm, where the speckle contrast is equal which is a reduction of 30%. On wafer LWR vs laser bandwidth for a 56nm line on a 120nm pitch test case data has been generated. This case was used in the qualification of the pulse stretcher2. Wafers have been processed with a fixed imaging pupil and mask CD with increasing laser bandwidth. This data will be reviewed, to demonstrate a reduction in local critical dimension uniformity (LCDU). The Authors will review simulations, experimental data and the process to develop a working imaging solution that further reduces LCDU.

In this work, we compared the performance of BF imaging in combination with a spin-on MOR and DF with CAR to generate hexagonal contact holes and understand the advantages obtained with each patterning approach in terms of dose and LCDU. CH patterns of pitches 38 and 34 nm were generated using SE EUV and LCDU decomposition was done to identify the main contributors to LCDU for both cases. Since the inherent properties of both resists are significantly different, we transferred the patterns into a relevant layer to do the final comparison AEI at pitch 38nm.

The AIMS® EUV system represents a unique piece of the EUV mask infrastructure for the qualification of the mask printing performance in the aerial image. To meet the industry requirements in the future, ZEISS started the development of a next generation EUV mask review tool, the AIMS® EUV 3.0. The system is based on the best-in-class optical concept proven for the current generation. The tool will support 0.33NA isomorphic and 0.55NA anamorphic imaging from the beginning. In this paper, we will introduce the concept of the AIMS® EUV 3.0 and present the current development status.

Patterning variability at tight metal pitch leads to a high risk for reliability failures. In 2023, we (Intel) demonstrated a novel EUV-based multi-patterning process enhanced by directed self-assembly (DSA) to scale metal pitch to 18 nm and below along with electrical validation data. The DSA process rectifies systematic and random variations in EUV patterns at 60% lower dose and in combination with spacer-aligned double patterning results in low-defectivity and low- variability metal patterns at the tightest pitch. Here we go further and demonstrate design flexibility, tone-inversion capability to enable subtractive metallization, sub-20nm metal end-to-ends, via and line resistances in line with model expectations, robust end-of-line standard cell chain and comb yields, and world-first demonstration of robust reliability data with matched dielectric breakdown and electromigration to a mature process at looser pitch.

Pellicles play a pivotal role as ultrathin, freestanding protective membranes within extreme Ultraviolet (EUV) lithography machines of ASML, safeguarding reticles against particle deposition. These ASML scanners subject these pellicles to challenging conditions, including a complex mix of EUV photons, hydrogen radicals, and plasma, at elevated temperatures which can induce chemical alterations and various forms of degradation, including dewetting and blistering of layers. Yet, the distinct impact of these conditions on pellicle lifetime remains underexplored. In this research, we meticulously investigated the individual effects of hydrogen radicals and vacuum EUV light on materials resembling EUV pellicles, while systematically varying the temperature. Our study concentrated on 50 nm thick semi-amorphous SiN thin films. Our findings reveal that exposure of pellicles to hydrogen radicals only did not induce any discernible chemical, structural, or morphological changes in the SiN thin film. In stark contrast, vacuum EUV photons triggered both chemical and morphological alterations, even at relatively low temperatures of 50°C.

In extreme ultraviolet lithography, multilayer roughness effects are a key contributor to mask-induced pattern roughness1. In particular, replicated roughness from the mask substrate results in a spatially dependent phase error that ultimately manifests as aerial image roughness at the wafer. In this paper, we utilize Monte Carlo methods to study the impact of multilayer roughness on the printing of two-dimensional patterns. We focus on the impact of multilayer roughness on both TaN absorber masks as well as attenuated phase shift masks, comparing roughness impact on each architecture at both 0.33 and 0.55 NA EUV lithography. We examine whether the modeled multilayer roughness explains observed patterning phenomena, with a focus on what level of remedy would be required for multilayer roughness effects to become negligible components of the patterning error budget.

Basic requirements for good patterns using extreme ultraviolet lithography (EUVL) are sensitivity, resolution, line edge roughness (LER), outgassing, etch resistance, defect density, and reproducibility. Among them, it has been proved that resolution, LER, and sensitivity (RLS) are interdependent with each other. The trade-off between RLS pose a critical challenge in the race towards device downscaling to 1 nm node. LER is the most important consideration to determine the manner in which EUVL will be employed. Recently, we develop a new EUV dry resist with organic-inorganic hybrid multilayer structures vertically tailored with several functional layers by using molecular layer deposition. Additionally, each layer includes a self-assembled organic monolayer to generate a vertical molecular wire structure. The hybrid multilayer resist shows high EUV sensitivity from the high EUV absorbing and reactive layers there. Furthermore, the vertical molecular wire structure of the hybrid resist generates exceptionally low LER.

An all-EUV dry resist technology offers a fundamentally new way to enable resist processing targeting differentiating capabilities for high NA lithography. Dry deposition of resists offers stochastic benefits with precise control over thickness and composition. Dry development enables in-situ tuning of development and also improves pattern collapse margin for higher aspect ratios. In this talk, we establish the progress of dry resist development toward extending the limits of single expose with 0.33NA EUV lithography. We assess electrical yield performance with a BEOL Cu-dual damascene test vehicle at aggressive 28nm and 26nm single expose metal pitches and correlate with defect metrology. We also present improvements in 26/28nm pitch line/space patterning and sub-40nm pitch contact hole patterning by optimization of process parameters such as underlayer, bake, dry development and pattern transfer.

Several stitching approaches are considered to secure patterning performance across the stitch boundary and at ASML Brion we are developing solutions to support patterning at resolution across the stitch. Sensitivity analysis is performed to quantify contrast, CD control, and pattern placement performance across the stitch boundary for holes and line/space layers and experimental CD control and experimental process capability and reticle patterning performance is presented and compared to the latest simulation and modelling capability using calibrated 0.33NA models and exposures. Especially important is to quantify cross talk of model accuracy errors, reticle CD errors, and placement errors in the stitching region where advanced models, scanner control and process design strategies are required.

To ensure successful mass production for GAA MBCFET structures and beyond, EUV overlay technology has advanced to withstand extreme process conditions. Commonly used method for its effectiveness was using overlay feedforward strategy to compensate upcoming critical layers such as ‘N+1’, or ‘N+2’ layer with current layer ‘N’ assuming the applied layers have kindred stack properties with identical overlay targets. Overlay feedforward strategy has been developed internally in great sophistication to significantly enhance on product overlay(OPO) proven also in mass production phase. However, it has been recognized that using aforementioned strategy to specific products rooting from GAA MBCFET structure may not be as beneficial as anticipated. In this paper, we would like to present the source of this strange phenomenon largely due to wafer warpage, in which we provide comprehensive solutions to measure, contain and permanently eradicate the originating in-coming process. After implementation of the authors' solution, overlay feedforward strategy demonstrated to be efficacious even for highly biased process excursions.

ASML NXE:3400 and NXE:3600D scanners are now commonly used for High Volume Manufacturing (HVM) of 7 nm to 3 nm logic devices as well as 10 nm class memory devices. In this paper we will share the latest performance of these systems, including excellent overlay, critical dimension (CD) control, stability, reliability, and high productivity Furthermore, we will describe the latest technology supporting the ASML roadmap for further improving cost of technology via increased productivity and share system qualification and performance data of the next HVM scanner, the NXE:3800E. Lastly the ASML NXE sustainability roadmap showing progress and steps towards a significant reduction in energy consumption per wafer exposure on NXE systems will be presented.

Extreme ultraviolet (EUV) lithography takes the forefront as a key nanopatterning technique in the current mass production of CMOS chips. EUV interference lithography (EUV-IL) is pivotal for photoresist development and scientific projects involving nanopatterning. These systems typically employ two or more transmission diffraction gratings on thin silicon nitride membranes. Coherent EUV light diffracts through the gratings, creating an interference pattern in the photoresist. However, challenges as reduced diffraction efficiency and complex nanofabrication for sub-10 nm patterning hinder the pursuit of the ultimate resolution. To this end, we report the latest results of our mirror interference lithography (MIL) setup that uses reflected light to overcome transmission-grating challenges. Two mirrors with a central stop create an interference pattern with grazing angle dependent pitch. We achieved resolutions down to 5 nm HP at EUV wavelength, marking a new resolution record in nanolithography. This method is valuable for testing photoresists and pattern transfer techniques for high- and hyper-NA EUV lithography, or fabricating high-resolution nanostructures for scientific purposes.

Recently progress of LPP EUV light source is remarkable. Ten years ago, power level is only several 10 W level. At present 250W power level is realized in semiconductor mass production factories1) by ASML. On the other hand, pioneer of this Unique technologies including; combination of pulsed CO2 laser and Sn droplets, dual wavelength pico second laser pulses for shooting and debris mitigation by magnetic field have been applied by Gigaphoton2). They have demonstrated high average power >300W EUV power with CO2 laser more than 27kW at output power in cooperation with Gigaphoton and Mitsubishi Electric3). In near future more higher power (>600W) EUV source is required to fit High NA (>0.55) lithography of semiconductor industry. In this paper we will discuss about the Sn plasma dynamics which dominate the EUV emission by using Tomson scattering (TS) measurement4. Recent TS results have revealed whole profiles of electron temperature and ion density in the EUV sources. These results mention that there is still sufficient potential to increase EUV output power and conversion efficiency in near future.

As the proportion of LWR/CDU in the EPE budget has tightened in recent years, its reduction has become a critical issue. Among many factors, contributions of resist and speckle play a key role in LWR/CDU. The authors therefore carried out a series of experiments in which the resist compositions and the speckle were controlled in order to validate the above points. The spatial frequency of the speckle was controlled by controlling the illumination conditions of the scanner in the experiments. The experiments not only clarified the contributions of resist and speckle, but also confirmed the contribution of the interaction between resist and speckle. We were able to use PSD analysis with the results of a simplified model-based Monte Carlo simulation to explain the interaction between resist and speckle. In addition, experimental results proved that LWR/CDU reduction can be achieved by reducing speckle and optimizing resist composition.

Gigaphoton has developed the advanced ArF immersion (ArFi) light source GT80A to enhance wafer productivity. GT80A operates at 6.75kHz, surpassing conventional ArFi light sources limited to 6kHz. Enhanced power supply modules offer reduced charging times and lower electricity consumption. The novel laser chamber design optimizes gas flow and minimizes acoustic wave impact, maintaining dose stability and reducing fluctuation of E95% bandwidth (E95) under a given repetition rate setting. A refined line narrowing module (LNM) tackles challenges at 6.75kHz, enhancing wavelength control. GT80A operates effectively at 6.75kHz while ensuring stability in dose, E95 and wavelength. The design also addresses optical component life duration, counteracting increased heat load effects to maintain seamless 6.75kHz operation without compromising availability.

Maximizing efficiency in complex laser systems by integrating machine learning and optimizing exchange parts. Challenges include reducing maintenance time, improving module lifetime, and implementing proactive maintenance through data analysis. Specific developments include hardware improvements, skill enhancements for service engineers, extending module lifetime, and data analysis for lifetime prediction.

Strong emission at the wavelength of 13.5 nm is obtained from laser-produced tin plasmas. Emission in shorter wavelengths in the 6 - 7 nm band can be obtained using gadolinium and terbium plasmas. The emission mainly arises from atomic 4d-4f and 4p-4d unresolved transition array (UTA). The emission spectrum from YAG laser-pumped plasmas shows a broad tail on the longer wavelength side, which is attributed to emission from multiple excited states. We calculate the emission spectrum based on the computational atomic data to investigate the condition to obtain high power with high spectral purity.

Mask shift double exposure (MSDE) is a method of patterning by exposing energy to the PR of the wafer twice consecutively without unloading the wafer and mask. It was confirmed that the first and second exposure energies are linearly summed, showing that the combination of the first and second exposure patterns allows more sophisticated patterning than one exposure. When the two exposure patterns are parallel lines in the MSDE approach, a 19 nm line CD is realized by precisely controlling the line CD according to the exposure interval between the two lines. In addition, when the two exposure patterns are orthogonal lines in MSDE, a 29 nm pillar pattern can be realized, which is beyond the limit of resolution of ArF immersion lithography.

As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at lithography and etch process and eliminate film-related defects. These approaches require improvements to the process chemicals and the lithography process equipment to achieve finer patterns. ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) technique has been developed and optimized to fulfil this novel development need. ESPERTTM has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews 23 nm pitch line and space and sub-40 nm pitch pillars which were realized by optimized illuminators with 0.33 NA single exposure, and we will show how ESPERTTM helped improve the minimum critical dimension size, defectivity, roughness and electrical yield at the finer patterns.

The 10 nm technology class DRAM devices have already advanced with different patterning schemes using EUV [1-3]. Such efforts rely heavily on the choice of the underlayers, resist and the source-mask optimized (SMO) illumination mode. In this work, these concepts were explored in a single mask solution to pattern 42 nm pitch, Local Interconnect and periphery landing pad (LILP). To provide a more industry relevant solution, the use of Chemically Amplified Resists(CARs) has been adopted to pattern pillars and line/space (LS) patterns simultaneously. In addition, the following parameters have been evaluated to achieve the best printability of the two types of structures: (i) CARs tailored for high and low dose process (CAR-A and CAR-B), (ii) different underlayers (UL0, UL1, UL2), (iii) post exposure bake (PEB) conditions to determine the effect of dose-to-size and impact on the local CD uniformity (LCDU) in pillars and line width roughness (LWR) for LS. The performance comparison of different process options was done based on roughness/LCDU and dose-to-size (D-t-s). This paper is organized as follows: 1. Experimental Method- Different combination of underlayers and resist screening using a single EUV source and mask. Optimization of the mask CDs and the overlapping process performance of pillars and LS based on the metrology inspection. 2. Underlayer performance- Choice of the underlayer based on printability performance and roughness/LCDU for a fixed resist coated on different underlayers. 3. Resist performance- Defect-free process window (PW) evaluation with different CAR coated on the best performing underlayer.

Extreme ultraviolet (EUV) lithography sources generate energetic tin ions. Accurate modeling of ion transport relies on knowledge of elastic scattering cross-section of tin ions against molecular hydrogen. This work uses available theoretical knowledge of elastic scattering found in literature, quantum chemistry modeling of the interaction potential between tin and hydrogen, and experimental scattering measurements of a tin ion beam to calculate the cross-section values. Furthermore, semi-classical collision calculations were used to calculate collision induced dissociation cross sections of tin ions and molecular hydrogen.

During operation of CO₂ drive lasers up to 60% of the CO₂ decomposes into CO. Gold can be used as a catalyst to reduce this decomposition to around 40%. CO₂ decomposition has a significant impact on laser efficiency and EUV production. Moreover, free O radicals create parasitic species such as Ox and NOx compounds. It is hypothesized that a secondary plasma source near the catalyst will increase O concentration near the catalytic surface, increasing the rate of CO oxidation. Species concentrations are measured using OES as a function of plasma power, gas mixture, and gas flow speed. The effect of an auxiliary surface wave plasma source is reported for tests with a heterogeneous gold catalyst installed.

Extreme ultraviolet (EUV) lithography sources use large amounts of tin to create ultraviolet light. Accurate modeling of neutral tin transport relies on knowledge of the diffusion coefficients of neutral tin through molecular hydrogen. This work experimentally determined the diffusion coefficients of tin through molecular hydrogen vapour at different tin temperatures and ambient pressures. A known amount of tin is evaporated into a pipe with a known flow profile at a known ambient pressure. Deposited tin is measured downstream of the pipe with a quartz-crystal microbalance (QCM). A variety of analytical and numerical coefficients were then compared in order to find the diffusion coefficient.

EUV Lithography is an important technology that drives semiconductor device miniaturization. It is currently undergoing high volume manufacturing (HVM) of 3 nm logic node and development of 2 nm node by leading-edge semiconductor manufacturers. EUV mask technology is becoming increasingly important factor for EUV lithography. Mask resolution requirement is under 25nm for 2nm node Technology node. DNP has developed the EUV mask process with using the low-sensitivity-high-resolution resist and multi beam mask writer (MBMW) and This process shows promising capability on the resolution for 2nm Logic technology. For A14 Technology need more high resolution mask, In this paper, we present a comprehensive study on mask processes that possess a resolution of 20nm or below and techniques aimed at enhancing lithography contrast.